RAIL Revision Or Appendage Document  (ROAD)

ROAD ID#:       12.1
ISSUE TITLE:    Clarity of Connectivity Types 
REQUESTER:      John Keifer, Intel Corporation
DATE SUBMITTED: September 15, 1997, September 26, 1997 
DATE ACCEPTED BY RAIL WORKGROUP:   October 30, 1997

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STATEMENT OF THE ISSUE:

It should be made clear near the beginning of the RAIL spec that there are 
three different types of connectivity and what the difference is between them.

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

Add to the Statement of Intent section between the second and third paragraphs
from the end, the following:

| There are actually three different types of connectivity.  They are
| described as the following:
|
|   1)  Logical connectivity - This is in the schematic netlist.  It has a
|       different net_name for each schematic connection.
|
|   2)  Physical connectivity - The artwork or layout physical connections
|       on the PCB board seen in the CAD tool.  Derived directly from the
|       schematic netlist.  However, not every logical net on the netlist
|       has a physical instantiation.
|
|   3)  Electrical connectivity - An electrical net consists of one or more
|       physical nets, each with a separate net_name, possibly attached with
|       one or more series devices.
|
| The keywords assuming electrical nets are given in the General syntax rules
| and guidelines for ASCII RAIL files section 10.
|

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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The Statment of Intent section explains the different types of connectivity 
as the following:

Logical connectivity (netlist)
and mechanical information (placements, footprints) will enter the EDA 
environment through other standard, previously defined mediums.

1) Schematic - original design drawing showing logical connectivity 
2) Netlist - normally compiled from the schematic, it contains a
                 complete ASCII text file of all logical connections
6) Artwork - physical circuit connections, derived by the layout process

General syntax rules and guidelines for ASCII RAIL files section explains 
the different types of connectivity as the following:

10)  Nets With Series Elements.  Defined keywords [Group Nets], [Topology],
     [Clocks], [Clock Skew], [Edge Sens], and [Budgets] may refer to signal 
     nets that contain "series elements".  Series elements (such as 
     resistors, inductors, diodes, jumpers, connectors, etc.)
     normally cause a single connection or "electrical net" to have two 
     or more net_names in a schematic or netlist.  In these cases,
     the RAIL file will seemingly refer to only one section of a net, when 
     actually the entire "electrical net" is intended.  The burden is 
     placed on the EDA software to recognize these situations, and apply 
     the data in these keywords to the larger "electrical net".

11)  RAIL file terminology glossary:
       net - a logical connection, that may or may not have a
               physical instantiation.
       net_name - the alphanumeric name given to a net (signal) in both a
               RAIL file and a netlist file.  In many places in a RAIL 
               file either net_name or group_name can be used to apply 
               constraints to one net or a group of nets.

These comments are separate details in different places in the RAIL file, 
and they are unclear and sometimes confusing.  There needs to be one place 
at the beginning of the RAIL spec which accurately and clearly describes 
each of the different types of connectivity to make the rest of the RAIL 
spec easier to understand.

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ANY OTHER BACKGROUND INFORMATION: