# Contents of iobuff.sp

...

.SUBCKT IO_IN OUT IN VDD VSSD1 IN VDD DD2 VSS IN DR1 IN 1 10

M1 OUT 1 VDD VDD pm L = 5U W = 120.00U

M2 OUT 1 VSS VSS nm L = 5U W = 50.00U .ENDS IO_IN

.SUBCKT IO_TEST_LOAD LOAD

R1 LOAD 1 50

V1 1 0 1.8

C1 LOAD 0 10p

.ENDS

XOUT 1 2 3 4 5 IO_OUT

XIN 6 1 4 5 IO_IN

XLOAD 1 IO_TEST_LOAD

VDD 4 0 5

VSS 5 0 0

VDATA 2 0 PULSE(0 5 0 10n 10n 50n)

VENA 3 0 5

RDUM 6 0 1e6

*simulator lang = spectre

model pm mos0 type=p

model nm mos0 type=n

model d diode

simulator lang = spice

The main circuit is a test fixture and must be commented out.

Previous slide | Next slide | Back to first slide | View graphic version

Notes:

The demo “iobuff.sp” desn’t have the main circuit stuff in red.