RE: standard loads on 66 MHz PCI

Why does PCI have three different test loads? To try to mimic some
aspect of actual operating conditions.

The minimum test load mimics the lightly loaded case: short bus wires,
minimum device capacitance.

The two maximum test loads model a driver sitting in the middle of a
long transmission line that has settled to the previous state's voltage.
Thus, when switching high-to-low, the bus is initially high, and looks
like a thevenin resistance of Zo/2 (both "halves" of the t-line in
parallel) to Vdd. While an infinitely long t-line may not be completely
"realistic," its purpose as a test load is to extract how well the
buffer switches such a load, before the reflection has returned.

Are multiple test loads an isolated case with the 66MHz PCI spec? Well,
33MHz PCI (at 3.3V signaling) uses it too.

Regards,
Andy Ingraham
Received on Mon Nov 9 12:25:50 1998