POWER_CLAMP for 3-state

From: Eric Hui <Erichui@genesis-microchip.com>
Date: Mon Aug 14 2000 - 15:13:42 PDT

This is not necessary a program-specific question. But just as a background info, I downloaded the program <<SPICE-to-IBIS conversion(IBISv2.1) by North Carolina State University>>, and I am trying Example 4.

I have a question about the "3-state" model. When I ran the conversion, I notice that the SPICE-to-IBIS program did the following to measure POWER_CLAMP:

1. Supply VDD=3.3V.
2. Supply VDD_clamp=5.0V.
3. Disable output (i.e. put in high impedance state).
4. Put input pin to high (+Vdd) = 3.3 V.
5. Sweep output pin voltage from (+Vdd_clamp)=5.0V to (+Vdd_clamp+Vdd)=5.0V+3.3V=8.8V, and measure the current at output pin.
6. Record the I-V table (using the vcc-reference-formula: V_table = Vdd_clamp - V_applied. e.g. -3.3V = 5.0V - 8.8V).

The converison ran fine, without any harming errors, and an IBIS file was generated.
I am now trying to use this IBIS file (as blackboxes) in my HSPICE simulation. My HSPICE simulator expects that when V_table = 0, the correspoinding current should be 0 amps.

When V_table = 0, V_applied 5.0V (see formula above). I am having a problem, because obviously there is a non-zero current when there is a drop of voltage (between 5.0V and 3.3V).

My question is:

Did the SPICE-to-IBIS measure the POWER_CLAMP incorrectly? or,
did my HPSPICE simulator expect something unreasonable (zero current at zero voltage)? or,
did I do something wrong?

Please reply. Any help will be greatly appreciated. Thanks in advance!

PS: My IBIS model is of version 2.1.
Received on Mon Aug 14 15:12:47 2000

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