Re[4]: IBIS Open Forum 1/6/95 Meeting Minutes

From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Date: Tue Jan 17 1995 - 16:26:01 PST

Text item:

Kumar,

Now I am starting to understand your thought process. However, I don't agree
with your suggestion, quote: "For a practically meaningful v-i verification...
...compare the resulting v-t with some reference waveform".

If you are trying to verify the I-V curve, don't use waveforms, because the
waveforms are not directly effected by the I-V curve. Waveforms are dependent
on rise/fall times, transmission line models (lossy or lossless), T-line length,
load capacitances, etc... None of which have much to do with DC. The only
thing you can do to verify an I-V curve is to look at the ledge voltage (if you
have a distinct one) of a waveform. However, you can get the same ledge voltage
with a pure resistor as the load (if its value represents your loading
impedance). Once you are at this point, you might as well just match the I-V
curve to a known Referece I-V curve, and be done.

Arpad

------------------------------------------------------------------------------

By standard load, I waa trying to indicate the following.

The ac v-t specifications include loads under whcih the measurements
were taken.
So if the siumulations reproduce the v-t behavior at those load conditions
then
they are self verifying and are pracically meaningful.

For a practically meaningful v-i verification, we have to drive a
reference load with the
device and then compare the resulting v-t with some reference waveform.
What is a useful refernce load. Is it daisy chain transmission line
with ten loads? Or is it a simple capacitor? In the past we have been
unable to come to agreement on identifying both the reference load
and waveforms.

This is what I meant by refernce loads for v-i verification.
>
> Kumar,
>
> I am still not sure what you mean by "standard load". When you
do a voltage
> sweep on a device, you are forcing the voltage while you are measuring the
> current. When yo do this sweep, you are actually "loading" the
device with the
> voltage source. You can look at that voltage source as an ideal,
0 Ohm source
> or as a Thevenin combination of an ideal source with a series resistor.
 Either
> way, you are sweeping between a certain voltage range at the output of the
> device to get an I-V curve, regardless of what R is in your Thevenin
circuit.
> Your I-V curve will be the same whether R in the Thevenin circuit
is small or
> large. You will just have to increase the sweep range of the voltage
source
> inside the Thevenin circuit for larger R values to get the same
sweep range at
> the pin of the device.
>
> What is the probelem? Am I missing something obvious?
>
> Arpad
>
> -----------------------------------------------------------------------------
-
>
> The problem with I-V checking is that there is no "standard" load as
> with V-T curves. We already went through this i-v standard load discussion
> and dropped it because
> of controvorsey. The reason I raised it because that I think that in
> signal integrity situations the dc I-V characteristic has more has
a dominant
> effect on the resulting waveforms and we have no reference to check against.
>
> >
> > Hello IBIS gurus,
> >
> > In the last minutes Kumar suggested DC checking (see quote below).
 I am not
> > sure what he means, but just as we can use V-T tables for AC checking,
> couldn't
> > the I-V curves be used for DC checking?
> >
> > Arpad
> > Intel Corporation
> >
> >
> > > Compliance
> > > Will pointed out that the V/T table can be used to as a type
of compliance
> > > test/sanity check. Kumar would like to see a DC check as well.
> >
> > > AR Kumar: Post an EGG for DC checking.
> >
> >
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> > Subject: IBIS Open Forum 1/6/95 Meeting Minutes
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Subject: Re: Re[2]: IBIS Open Forum 1/6/95 Meeting Minutes
To: ibis@vhdl.org, Arpad_Muranyi@ccm.fm.intel.com
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From: cpk@cadence.com (C. Kumar)
Date: Tue, 17 Jan 95 14:04:03 -0500
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Received on Tue Jan 17 16:32:00 1995

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