Subject: RE: Clock limitations on IBIS simulation.
From: Muranyi, Arpad (arpad.muranyi@intel.com)
Date: Tue Jan 08 2002 - 15:56:05 PST
To All,
After my posting Scott sent me a private message and reminded
me of something I didn't think of when I replied, and he is
absolutely correct. Here is his message:
>Arpad,
>
>you'll never be able to account for non-ideal power and ground
>collapse.
>
>Scott
Thanks Scott for reminding me (and now everyone else to that).
Arpad
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-----Original Message-----
From: Muranyi, Arpad
Sent: Tuesday, January 08, 2002 11:34 AM
To: ibis@eda.org
Subject: RE: Clock limitations on IBIS simulation.
Scott,
I am not sure that I agree with you. If you are referring to
"IBIS simulation" in which you use the package (and perhaps
the EBD) model as provided by the IBIS model, yes, I agree.
But if you refer to an IBIS buffer model used with an external
package and PCB model (in which the return path, etc. are
correctly modeled) then must I disagree. I believe it is
possible to account for the return path correctly using an
IBIS buffer model if the package and T-lines include the
return path.
Arpad Muranyi
Intel Corporation
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