RE: [IBIS-Users] RE: [IBIS] RE: IBIS model behavior between Vinh and Vinl input

From: Akhilesh CHANDRA <akhilesh.chandra_at_.....>
Date: Fri Jan 04 2008 - 02:46:11 PST
  All the manufacturer extract the Vinh and vinl values at one process,
voltage and temperature. I don't think if we extract vinh-vinl with spice
simulation at one process voltage temperature then it have different value
in the manufacturing process. 

  Today few IBIS simulator show X(0.5V) between reference values while I
don't see X in the real circuit design. It show something is wrong . I am
agree with you all the designs shouldn't confirm the arbitrarily designated
state but now we will need to think what is the correct behavior of IBIS
model between reference values.

Regards
Akhilesh
   

-----Original Message-----
From: Tom Dagostino [mailto:tom@teraspeed.com] 
Sent: Friday, January 04, 2008 3:04 PM
To: 'Akhilesh CHANDRA'; 'Muranyi, Arpad'; ibis@server.eda-stds.org;
owner-ibis-users@server.eda.org; ibis-users@server.eda.org
Subject: RE: [IBIS-Users] RE: [IBIS] RE: IBIS model behavior between Vinh
and Vinl input

Be careful.  IBIS uses the manufacturer's specified Vinh and Vinl.  They are
the points where the part is guaranteed to switch.  As Arpad points out the
actual switching point could be different and very well changes with
temperature, voltage and process though modern manufacturing processes make
the actual switching points more consistent from part to part.  Timing
should be measured to the points that are in the datasheet.

But having all simulators default to some arbitrary state when the input is
between the reference levels is setting the user up for failure.  People
tend to assume if the simulator says X, X is real.  If they don't see X in
the real circuit then there is something wrong.  Not all parts will conform
to some arbitrarily designated state.

Digital parts are not made to operate with their inputs between Vinh and
Vinl.  Most parts have specifications that state the minimum slew rate
(input risetime/falltime) as the input to the part transitions between the
two reference levels.  The actual output of an input buffer for a given
input voltage between Vinl and Vinh will change depending on the internal
noise of the IC, the noise on the input, process, temperature, voltage,
phase of the moon, crosstalk, etc.

Tom Dagostino
Teraspeed(R) Labs
13610 SW Harness Lane
Beaverton, OR 97008
503-430-1065
503-430-1285 FAX
tom@teraspeed.com
www.teraspeed.com

Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
401-284-1827 


-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf
Of Akhilesh CHANDRA
Sent: Friday, January 04, 2008 12:23 AM
To: 'Muranyi, Arpad'; ibis@server.eda-stds.org;
owner-ibis-users@server.eda.org; ibis-users@server.eda.org
Cc: Akhilesh CHANDRA
Subject: RE: [IBIS-Users] RE: [IBIS] RE: IBIS model behaviour between Vinh
and Vinl input

Hello Arpad,

  I got your point. As I understood IBIS model of a receiver is measurement
model. it compare the incoming waveforms against Vinh and Vinl.  If it is
above Vinh, we have a logic "1" ("true"), if it is below Vinl, we have a
logic "0" ("false") and between vinh and vinl it have logic X.

  IBIS specs don't define that how logic X represent in IBIS simulation, due
to this different simulator give different behavior for X. In my view we
will need to define how logic X represent in IBIS model simulation. It will
help to align all the simulator results.

Regards
Akhilesh

-----Original Message-----
From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Muranyi, Arpad
Sent: Friday, January 04, 2008 12:34 PM
To: ibis@server.eda-stds.org; owner-ibis-users@server.eda.org;
ibis-users@server.eda.org
Subject: [IBIS-Users] RE: [IBIS] RE: IBIS model behaviour between Vinh and
Vinl input

Akilesh,

I don't think you understood my previous answer.  On the other hand, I am
not sure I understand everything you say either, so I will attempt to
describe it once again.  Let me know if I didn't answer your question, but
please be a little more crisp with your words, because I have a hard time to
understand what you are writing.

A SPICE receiver model will give you a WAVEFORM on its output.
This waveform will be a smooth waveform.  It will switch states when the
input goes over the threshold value of the input amplifier.
This threshold voltage is not the same as the IBIS Vinh and Vinl parameters.
In the good old 5 volt days the receiver could switch a few hundred mV
around 1.5 volts, while the TTL specification was 0.8 and 2.0 volts for Vinl
and Vinh.  The specification was usually set to a wider range than the
actual threshold for various reasons.

In IBIS we don't model the actual threshold behavior of the receiver.
(You could if you used [External Model], but that is a different story).
The IBIS receiver is really nothing more than a measurement model.  It
doesn't simulate the receiver's actual reactions to the incoming waveform,
and most importantly it doesn't give you an analog waveform that resembles
the output waveform of the actual receiver.

You can consider the output of the IBIS receiver as a logic output of an
ideal comparator, comparing the incoming waveforms against Vinh and Vinl.
If it is above Vinh, you get a logic "1" ("true"), if it is below Vinl, you
get a logic "0" ("false").  The transition is abrupt, theoretically with a
perfectly vertical edge.  Do not expect to see a smooth waveform here.

Since most IBIS simulators represent the output of a receiver as a waveform,
you will most likely get a 0 volt or a 1 volt signal instead of a logic
"true" or "false".  But the meaning is the same.

The remaining question is what should the output of the receiver be when the
input waveform to the receiver is between Vinh and Vinl.
The problem is that the IBIS specification doesn't describe this in great
detail.  If we go by the example that is in the IBIS spec, where the
comments say the following:

Vinl = 0.8V | Input logic "low" DC voltage, if any Vinh = 2.0V | Input logic
"high" DC voltage, if any

we could conclude that anything in-between Vinh and Vinl is neither logic
"high" or "low", i.e. it is an undetermined state "X".

I have seen implementations where the output of the receiver would switch
when the waveform goes above Vinh on a rising edge, and goes below Vinl on a
falling edge.  This gives you a hystersis type result which is not
necessarily correct, because the receiver may lose its valid logic output as
soon as the input waveform enters the region between Vinh and Vinl.  I
personally prefer the undetermined state on the output of the receiver "X".
But how can this be represented in an analog simulator which gives us a 1 or
0 volt output?  In that case I would suggest that the receiver's output
should go to 0.5 volt when the input waveform is between Vinh and Vinl,
indicating that this is the undetermined condition "X".

I hope this helps,

Arpad
=======================================================================



-----Original Message-----
From: Akhilesh CHANDRA [mailto:akhilesh.chandra@st.com]
Sent: Thursday, January 03, 2008 9:45 PM
To: Muranyi, Arpad; ibis@server.eda-stds.org;
owner-ibis-users@server.eda.org; ibis-users@server.eda.org
Cc: Akhilesh CHANDRA
Subject: RE: [IBIS] RE: IBIS model behaviour between Vinh and Vinl input

Hello Arped, 

    Thanx for your reply. In the design spec output can't switch between
vinh and vinl values. And we run simulation with spice then design behave
same way and give smooth transition as the device does. I am using ELDO as
simulator to run the IBIS simulation it show horizontal line (other
simulator show different result) between vinh and vinl values it shows
mismatch between IBIS and spice behavior. Do you think the behavior of
simulator is correct.

   In my view we will need to define IBIS behavior between vinh and vinl
values otherwise each EDA vendor do it by his own algorithm and it create
confusion at the application end.

Regards
Akhilesh

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On Behalf
Of Muranyi, Arpad
Sent: Thursday, January 03, 2008 9:47 PM
To: ibis@server.eda-stds.org; owner-ibis-users@server.eda.org;
ibis-users@server.eda.org
Subject: [IBIS] RE: IBIS model behaviour between Vinh and Vinl input

Akilesh,

A SPICE model does what the device does (more or less).

An IBIS model's Vinh and Vinl does what the input specification tells you
when you look at a SPICE waveform and try to decide whether the waveform you
got was good enough to consider logic high or logic low.  IBIS does not
describe how the device behaves between Vinh and Vinl.

Arpad
================================================================= 

-----Original Message-----
From: Akhilesh CHANDRA [mailto:akhilesh.chandra@st.com]
Sent: Thursday, January 03, 2008 4:22 AM
To: ibis@server.eda-stds.org; Muranyi, Arpad;
owner-ibis-users@server.eda.org; ibis-users@server.eda.org
Cc: 'akhilesh chandra'
Subject: IBIS model behaviour between Vinh and Vinl input


 


 Hello Experts,

   I am using IBIS model of hysterics cell. In my model Vinh and Vinl have
different values as per design specs. When I run it with one of the
simulator then it show output at constant voltage(VDDE/2) between Vinh and
vinl inputs, while spice show continuous behavior with same simulator so
there is big mismatch between IBIS and spice result.
   Can anyone explain us what IBIS standard say about output behavior
between Vinh and Vinl input values.

Regards
Akhilesh



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Received on Fri Jan 4 02:47:02 2008

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