Re: standard loads on 66 MHz PCI

Hi Greg,

I ran into this exact problem when I was trying to set up a simulation
environment for the 66 MHz PCI bus. Fortunately, the IBIS simulator I am using
allows me to choose whether I want the buffer delays to come from a simulation
into the standard load circuit from the IBIS model or from time values which I
directly give to the simulator. So what I did was use Spice to measure the rise
and fall delays into their respective standard load circuits; I then gave those
Spice generated numbers to my IBIS simulator. Not an ideal solution, but a
workaround that worked good enough.

Unfortunately, this solution doesn't help you much if you can't directly give
buffer delays to your simulator. The ideal solution would be to enhance the
IBIS spec to allow for a unique standard load circuit for both the rising and
falling edges; that is, if this is a common problem. Or is this pretty much an
isolated case with the 66 MHz PCI spec?

Regards,

Tay Ansari
Sun Microsystems

>
> From: Gregory R Edlund <gedlund@us.ibm.com>
> To: <ibis-users@vhdl.org>
> Subject: standard loads on 66 MHz PCI
>
> A question came up here at IBM today that I could not answer. Has anyone run
> into this?
>
> The 66 MHz PCI bus spec has a different standard load for rising and falling
> edges. (10 pF and 25 Ohms to gnd for rising OR 10 pF and 25 Ohms to Vcc for
> falling.) As I read version 3.1 of IBIS, it only allows one value of Vref per
> [Model] keyword. This seems to make the 66 MHz PCI driver unable to be
> implemented in IBIS, at least if you want to do timing analysis. I wouldthink
> someone else probably encountered this already. How did you get around it? Or
> am I missing something?
>
> Much thanks in advance.
>
> Greg Edlund
> Advisory Engineer, AS/400 System Timing
> IBM
> 3650 Hwy. 52 N, Dept. HDC
> Rochester, MN 55901
> gedlund@us.ibm.com
>
Received on Mon Nov 9 08:26:34 1998