Re: standard loads on 66 MHz PCI

Greg,

This is a good question. I've thought about it too. I've seen
evidense that no one knows how to handle it. I have yet to see an
IBIS file of a PCI component with the timing reference load specified.
There is one more problem. There is another load for min time. The
advice to uncomment the appropriate load and rerun simulation (from
Arpad) is about the only work around. I wonder if we can change the
PCI spec or at least come up with a standard PCI test load to include
in IBIS. Does anyone know WHY PCI has three different timing test
loads? I think that is an important question before we can come up
with an appropriate test load for IBIS.

Regards,
Weston Beal

> From: Gregory R Edlund <gedlund@us.ibm.com>
> To: <ibis-users@vhdl.org>
> Subject: standard loads on 66 MHz PCI
> Date: Fri, 6 Nov 1998 18:44:27 -0500
>
> A question came up here at IBM today that I could not answer. Has anyone run
> into this?
>
> The 66 MHz PCI bus spec has a different standard load for rising and falling
> edges. (10 pF and 25 Ohms to gnd for rising OR 10 pF and 25 Ohms to Vcc for
> falling.) As I read version 3.1 of IBIS, it only allows one value of Vref per
> [Model] keyword. This seems to make the 66 MHz PCI driver unable to be
> implemented in IBIS, at least if you want to do timing analysis. I would think
> someone else probably encountered this already. How did you get around it? Or
> am I missing something?
>
> Much thanks in advance.
>
> Greg Edlund
> Advisory Engineer, AS/400 System Timing
> IBM
> 3650 Hwy. 52 N, Dept. HDC
> Rochester, MN 55901
> gedlund@us.ibm.com
>
Received on Mon Nov 9 11:09:26 1998