Re: Diode Modeling in SPICE

Hello Silvia:

   It's not clear to me from your description if the problem is with the
active curves [Pullup]/[Pulldown] or diode curves [Gnd Clamp]/[PWR clamp],
but if it is the diode curves you may want to add some bulk and metalization
resistance to your model. In that past, that has done the trick for me.

    Regards,
    Stephen Peters
    Intel Corp.

> Hello IBIS model makers !
>
> I have a 5V CMOS I/O tristate-able buffer I'm trying to model. The IBIS
> curves generated by s2ibis2 are a very good match
> to measured data between 0.7v up to about 5.9v. But between -5V to 0.7v
> and 5.9v to 10v the curves deviate quite a bit.
> I've disabled the parasitic diodes in the nmos and pmos device models (
> IS=0 ) and added n+ and p+ parasitic diodes to the
> netlist. I've been playing with the n+ and p+ diode model (level 3)
> parameters ( n, js, ivb, area, pj ) trying to match SPICE
> results to measured data with limited success.
>
> Are there any suggestions for other model parameters to tweek, or maybe
> there is something going on with the s2ibis2 SPICE
> sim limits/parameters I'm not aware of ?
>
> Thanks,
> The time you spend helping me out is greatly appreciated !
>
> Silvia Montoya
> email : silvia.montoya@actel.com
Received on Fri May 14 08:49:48 1999