Need to double-check this. It seems that there are standard
logic components which, on output, sense the output voltage
and adjust drive current in response.
No, I don't mean bus hold. These parts drive LOW hard when
the output voltage is above a certain threshold and cut the
drive when the output is below that threshold. Rising-edge
drive is similar.
Yes, I know that this is of dubious stability. Nobody asked
me if they should do it this way, but the manufacturers want
to make this a JEDEC standard and I'm trying to help them
put together an IBIS model. Which, as far as I can tell, is
possible using
Submodel_type Bus_hold
and having negative currents in the [Pulldown] and [Pullup]
tables.
1) Have I missed a better way to do this?
2) Will this be legal?
3) Will this break EDA tools?
-- D. C. Sessions ibis@lumbercartel.comReceived on Thu Aug 31 11:29:39 2000
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