RE: What is the difference between C_comp and C_pin?

Theoretically it should have an effect on both. The problem is that in the
current IBIS specification there is no mention about where the C_comp is
connected. Here is what I mean:
 
Consider a complementary buffer which has both pullup and pulldown
transistors.
Both of these transistors have a parasitic capacitance between drain and
source.
These capacitors can be viewed as two series capacitors between power and
ground.
However, the midpoint is connected to the pad. So it will effect the signal
as
well as power/ground bounce, plus act as an on die decoupling capacitance.
 
The problem is that because IBIS doesn't tell you how C_comp supposed to be
divided up between power and ground, most implementations just put it
between
the pad and ground. This may load the signal, but will not account for the
supply bounce correctly. There is a BIRD which addresses this issue which I
hope will be voted on soon.
 
Arpad Muranyi
Intel Corporation
============================================================================
===
 
 
 
-----Original Message-----
From: DORIN OPREA [mailto:dorin.oprea@alcatel.com]
Sent: Wednesday, June 14, 2000 6:55 AM
Cc: 'ibis-users@eda.org'
Subject: Re: What is the difference between C_comp and C_pin?

Is C_comp a parameter characterizing the chip (good for power-ground
bounce) and
 is also a parasitic on the buffer output (bad for signal speed) or is only
the parasitic on the buffer output ?

Thanks
  
  
  

"Dunbar, Tony" wrote:

Olli,

There are some REAL experts on IBIS out there that I hope will jump in and
answer your questions and, perhaps, correct and add to mine. Here goes:

You are correct - as you wrote, "C_comp comprises all of the capacitance of
a die seen from the pad." C_pin (or C_pkg, if C_pin is not defined) is the
capacitance of the packaging and interconnect that the die is packaged in
(if it is packaged). Suppose the same die is available in a couple or more
different packages (e.g. plastic or ceramic, SSOP or PQFP), then "good" .ibs
files for each should be expected to have the same values of C_comp but
different values of C_pkg/C_pin. If you were mounting the bare die on an
MCM, C_pkg/C_pin (and L_pkg/L_pin and R_pkg/R_pin) would be totally
different again. At the end of this text I have appended an example from the
Interconnectix Standard Library. The example is an AMD PAL. The basic
silicon is the AmPAL18P8 but in two different packages. Hence, the library
.ibs file has [Component] AmPAL18P8BP and [Component] AmPAL18P8BJ. Please
see how C_pkg/C_pin differ but C_comp is the same. Please also note the
significant C, L and R value differences between the packages. For faster
and faster edge rates, these packaging effects cannot be ignored and they
could make the difference between a working design and a non-working design.

One thing that's worth noting that might give an indication of the separate
nature of C_pkg/C_pin and C_comp is that C_pkg/C_pin are [Component] or
[Package] sub-parameters in the IBIS file but C_comp is a [Model]
sub-parameter.

So, C_pin is not supposed to be part of C_comp. Where they are often
effectively included together is in a component datasheet. Most times, the
vendor quotes a total pin capacitance value. Sometimes, it is required to
reverse engineer an IBIS file for a component using the datasheet, perhaps
with a V-I curve printed on the datasheet. You may then wish to create a
C_pkg element and a C_comp element from the Ctotal number. A rule of thumb
to work to that I got from Bob Ross is to apportion the Ctotal something
like C_comp=(Ctotal*0.85) and C_pkg=(Ctotal*0.15). Again, others PLEASE
comment.

In general, an IBIS simulator should not sum (or lump) C_pkg/C_pin with
C_comp because, in the general case, there are other interconnect circuit
elements between them (e.g. L_pkg and R_pkg) and summing them directly
together would be like collapsing a distributed element network into a
lumped one. Sometimes that gets you close enough, but not always. This may
be a simulator time-step and resolution issue. This is an important fine
detail aspect that I invite the simulator experts to comment on.

I hope this helps and stimulates other comments. Here's the example data:

[Component] AmPAL18P8BJ
[Manufacturer] AMD
[Package]
| variable typ min max
R_pkg .078ohms NA NA
L_pkg 3.58nH NA NA
C_pkg .884pF NA NA
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
1 I Z188249_IN .076 3.3n .8p
2 I Z188249_IN .078 3.5n .87p
3 I Z188249_IN .08 3.8n .94p
4 I Z188249_IN .08 3.8n .94p
5 I Z188249_IN .078 3.5n .87p
6 I Z188249_IN .076 3.3n .8p
7 I Z188249_IN .078 3.5n .87p
8 I Z188249_IN .08 3.8n .94p
9 I Z188249_IN .08 3.8n .94p
10 GND GND .078 3.5n .87p
11 I Z188249_IN .076 3.3n .8p
12 I/O Z188249_BI .078 3.5n .87p
13 I/O Z188249_BI .08 3.8n .94p
14 I/O Z188249_BI .08 3.8n .94p
15 I/O Z188249_BI .078 3.5n .87p
16 I/O Z188249_BI .076 3.3n .8p
17 I/O Z188249_BI .078 3.5n .87p
18 I/O Z188249_BI .08 3.8n .94p
19 I/O Z188249_BI .08 3.8n .94p
20 VCC POWER .078 3.5n .87p
...
[Model] Z188249_BI
Model_type I/O
Vinl=800.0mV
Vinh=2.000V
Vref=3.305V
Rref=132.2ohms
Cref=50.00pF
Vmeas=1.500V
C_comp 8.000pF NA NA
|
...
[Component] AmPAL18P8BP
[Manufacturer] AMD
[Package]
| variable typ min max
R_pkg .216ohms NA NA
L_pkg 5.76nH NA NA
C_pkg 1.29pF NA NA
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
1 I Z188250_IN .232 9.76n 1.87p
2 I Z188250_IN .224 7.26n 1.58p
3 I Z188250_IN .216 5.26n 1.29p
4 I Z188250_IN .208 3.76n 1.0p
5 I Z188250_IN .2 2.76n .71p
6 I Z188250_IN .2 2.76n .71p
7 I Z188250_IN .208 3.76n 1.0p
8 I Z188250_IN .216 5.26n 1.29p
9 I Z188250_IN .224 7.26n 1.58p
10 GND GND .232 9.76n 1.87p
11 I Z188250_IN .232 9.76n 1.87p
12 I/O Z188250_BI .224 7.26n 1.58p
13 I/O Z188250_BI .216 5.26n 1.29p
14 I/O Z188250_BI .208 3.76n 1.0p
15 I/O Z188250_BI .2 2.76n .71p
16 I/O Z188250_BI .2 2.76n .71p
17 I/O Z188250_BI .208 3.76n 1.0p
18 I/O Z188250_BI .216 5.26n 1.29p
19 I/O Z188250_BI .224 7.26n 1.58p
20 VCC POWER .232 9.76n 1.87p
...
[Model] Z188250_BI
Model_type I/O
Vinl=800.0mV
Vinh=2.000V
Vref=3.305V
Rref=132.2ohms
Cref=50.00pF
Vmeas=1.500V
C_comp 8.000pF NA NA
...
[End]

Regards,
Tony Dunbar
Mentor Graphics/ICX

-----Original Message-----
From: Olli Timonen [ mailto:Olli.Timonen@tellabs.fi
<mailto:Olli.Timonen@tellabs.fi> ]
Sent: Tuesday, June 13, 2000 9:35 AM
To: ibis-users@eda.org
Subject: What is the difference between C_comp and C_pin?

Hi!
I am a bit confused with C_comp. As I understand it, C_comp comprise all the

capacitance of a die seen from the pad. What is then the purpose of C_pin
(or
C_pkg if not defined)? Isn?t capacitance of C_pin included in C_comp? Does
simulator sum C_comp and C_pin together or does C_comp override C_pin or...?
Received on Wed Jun 14 08:35:09 2000