Hi Cyrille.
Basically the IBIS IO pad model should an electrical "black box".
Thus in your case I would recommend creating a new spice
model, i.e. also a new IBIS model.
Dan.
cyrille.cathelin@philips.com wrote:
> Hello,
>
> As I am developing an IBIS model for a chip I have a question to submit :
> If one of the pin is connected to two buffers in parallel (the same buffer model for each):
> Is it a solution in the IBIS norm to indicate the pin is conected to two buffers in parallel or should I develop a specific pad model for this structure?
>
> Thanks for an answer
>
> Cyrille CATHELIN
> IC Design Engineer Philips Semiconductors
> Business Line Digital Media - DVI 2, rue de la girafe - BP 5120
> Phone : +33 (0)2 31 45 31 73 14079 Caen Cedex5 - France
> e-mail : cyrille.cathelin@philips.com
-- \\|// (o o) ~~~~~~~~~~~~oOOo~(_)~oOOo~~~~~~~~~~~~~~~~~~~ Dan Aleksandrowicz Galileo Technology Mercaz Ofek 1 (Building B') Northern Industrial Zone, LOD 71293, ISRAEL email:dan@galileo.co.il Tel: +972 8 9247555 (- Ext. 324 |__| Fax: +972 8 9247554 |__| #|oo| |--| ___ _ _ |--| | | |\ |oo|) /\ __ \\ \\ |------------\| #|--\ _||- ____\ \__\\_\\__|_||_________________\___| |__v-___ \ / \ "Smoke on the water. Fire in the sky." / ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Received on Wed Nov 29 02:04:47 2000
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