the 4 V-t curves of IBIS 2.1

Betty,

Imagine a standard push-pull CMOS output driver with a PMOS pull-up device
and an NMOS pull-down device. In a behavioral model, you have information
about the Ids vs. Vds characteristics of these transistors, but you don't
know what their gate voltages look like as a function of time. Using the
four V-T tables, a behavioral simulator can cleverly deduce when to
"activate" the I-V tables in time to make the behavioral simulation look as
much like the real circuit as possible. A good example of this is crowbar
current. I/O circuit designers will often time-shift the gate voltage
waveform of the PMOS device with respect to the NMOS device to keep both
devices from being on at the same time. This minimizes the amount of
current shooting from Vdd to Vss and thereby minimizes noise.

Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com
---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
09/27/2000 04:41 PM ---------------------------

"Betty Luk" <Betty@genesis-microchip.com> on 09/27/2000 03:39:34 PM

To: <ibis-users@eda.org>
cc:

Subject: the 4 V-t curves of IBIS 2.1

Hello,

Why do we need four V-t curves to describe the rising and falling edges of
a CMOS buffer (as described in the IBIS cookbook)?

Many thanks,

Betty Luk

IC Technology
Genesis Microchip Inc.
165 Commerce Valley Dr. W.
Thornhill, Ont. L3T 7V8
(905) 889-5400 x2256

 
Received on Wed Sep 27 14:54:08 2000