Re: the 4 V-t curves of IBIS 2.1

Hi all,

The previous document had "Cadence Confidential" on it - which it isn't. My apologies. This copy has been corrected.

Todd.

At 06:59 PM 9/28/2000 -0700, Al Davis wrote:
>On Wed, 27 Sep 2000, Betty Luk wrote:
> > Why do we need four V-t curves to describe the rising and falling
>edges of a CMOS buffer (as described in the IBIS cookbook)?
>
>I assume you mean 2 per edge.
>
>One per edge describes what it does with a particular load. What it
>does into any other load is a guess.
>
>By supplying more than one waveform per edge, with different loads, it
>is possible to represent changes in the output resistance in the
>driver, in addition to the voltage.
>
>Usually, if you can provide 2 tables per edge, the best loads are to
>use the same resistance in both cases, but connect one to ground and
>the other to the power supply. To see why, consider that the typical
>driver consists of a pull-up device and a pull-down device. A
>resistor from the terminal to ground will tend to swamp out the
>pull-down device, and characterize the pull-up device fairly well. A
>resistor to power will do the opposite. Usually, the best resistance
>to use is as close as possible to the load it will actually drive.

    Todd Westerhoff
    Product Marketing Director | High Speed Systems Design | Performance Engineering
    Cadence Design Systems | 270 Billerica Road | Chelmsford, MA 01824
    
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