RE: zero risetime in the IBIS model

Jason,

One subtle point here is whether, or not, the [Model] that has this dV/dt_r
parameter also has waveform tables. If it does, the [Ramp] parameters should
be ignored by the simulator, anyway.

Neverthless, as has been suggested already, I would also strongly encourage
you to throw the model back at the vendor that supplied it.

This sort of clumsy or outright bad modeling continues in part, I believe,
because we, as consumers, tweak this and change that without letting our
suppliers know they are producing garbage. Sorry to rant on, but this is a
pet subject of mine because it wastes too much of my time and WAY TOO MUCH
of my customers' time. If it was a part for my car brakes that didn't quite
fit, what would I do? Closer to the point, if it was a VHDL model that
wasn't quite right and the ASIC didn't work, what would you and your
management do.

Signed,
Mr. Angry
(Tony Angry, that is!)

-----Original Message-----
From: Jason Leung [mailto:jleung@cid.alcatel.com]
Sent: Wednesday, April 04, 2001 8:59 AM
To: ibis-users@eda.org
Subject: Re: zero risetime in the IBIS model

Hi everyone:
I am trying to verify a IBIS model which consists of a zero rise time
for the driver:
| variable typ min max
dV/dt_r 0/0 0/0 0/0
dV/dt_f 2.0448/0.4029n 1.8546/0.4176n 2.1792/0.4102n
R_load = 50.0000

My question is :does anyone know how the IBIS translator going to handle
this situation??
thanks alot
Best Regards
Jason Leung
 
Received on Wed Apr 4 08:34:34 2001