[IBIS-Users] Re: V-t curves offset

Hello Ramiro:

Here are some additional comments to those already given.

The input stimulus transition time can be a factor contributing
to delay mismatches. Based on the IBIS model, the transition
might be triggered at the Vinl or Vinh values, at (Vinh+Vinl)/2
or at the 50 percent point of a 0 to 1 stimulus. Any of these
"model" thresholds could differ from the actual transistor model
threshold and contribute to ramp stimulus delay differences. So
some of the response below depends on the IBIS simulation tool,
the threshold switching details of the IBIS model, and also what
analysis you wnat to do.

Bob

RODRIGUEZ_LECONA_RAMIRO wrote:

> Hi all,
> I'm working with IBIS models validation and I have a problem
> correlating the IBIS model with transistor level buffer in HSPICE. I
> simulate both buffers with the same conditions (same load, temperature,
> voltage supply) and the rising/falling edges of the outputs are equal
> but there is a delay between IBIS model output waveform and transistor
> level buffer output waveform. I shift the V-t Tables in the IBIS model
> to compensate the delay and the output waveforms are matched but this
> occurs when the input signal has rising/falling times equal to the
> rising/falling times used to extract the IBIS model, if I use a input
> signal with rising/falling times lower than the rising/falling times
> used to extract the V-t curves then the buffer implemented with the IBIS
> model has again a delay.
> What happens?
> How can I understand this? How can I avoid this delay?

As noted above the input stimulus rate along with threshold switching
mismatch can contribute to delay differences.

We would need more information about the reference SPICE model to
answer if you need to do anything. For example if the input to the
model is really a "core" input, you might just use very fast ramps
to generate the IBIS model and do the comparison. If the SPICE model
input mimics an Input used to stimulate the buffer, then the
threshold differences might be the problem. You could tune the
Vinh and Vinl (Spec. limit values) to actual threshold levels in
the transistor model. However, for other reasons, you may want to
use the SPECIFICATION thresholds (with delay mismatches) for better timing
corner analysis per spec. limits than you would get from the transistor
model with a more limited range in its thresholds.

> Or this phenomenom is normal because the important thing is the edge
> waveform (buffer switching behavior) and the delay obtained is not
> relevant?

For some applications the timing test load reference simulations would
compensate for delay differnces based on different input stimulus
rate.

> Or the V-t curves obtained with specyfic rise/fall times are only
> valid to simulate buffers with input signals with the same rise/fall
> times ?

For reasons given above, I would expect some minor delay differences
for different input stimulus rates.

> Thanks.
> Regards.

-- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
503-750-6481                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com
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