IBIS-USERS - EIA IBIS Open Forum Users Activity: RE: [IBIS-Users

From: Tom Dagostino <tom@teraspeed.com>
Date: Tue Oct 12 2004 - 22:41:29 PDT

Aubrey

Overclocking can happen to any correctly constructed IBIS model, just push
the frequency higher. To a model that is incorrectly built it is easier to
accomplish this. The delay is still important and you really need to
calibrate the model via the Timing Test Load as Lynne points out.

I don't think its a good idea to adjust the input of the buffer in SPICE to
get even delays in the output. That is not how the buffer really works.
The buffer may have characteristics that for instance would cause a 50% duty
cycle clock to come out not 50%. Playing games with the stimulus to match
outputs could mask that characteristic.

Tom Dagostino
Teraspeed Consulting Group LLC
503-430-1065
tom@teraspeed.com
www.teraspeed.com

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Aubrey_Sparkman@dell.com
Sent: Tuesday, October 12, 2004 9:19 PM
To: tom@teraspeed.com; nitin.bhagwath@hp.com; rlecona@siu.buap.mx;
ibis-info@eda.org; ibis-users@eda.org
Subject: RE: [IBIS-Users] V-t curves offset

Tom,
I was talking about adjusting edges which are not very far apart, say
less than 10% of the total cycle time. I'm sure you are much more
experienced in buffer modeling than I, but your example sounds like
"over-clocking" the buffer; Arpad and others have discussed why this is
not a good thing.

I agree that "In a properly constructed output model the delay is
minimal"; I think this is what Ramiro is trying to do.

Aubrey Sparkman
Enterprise Engineering Signal Integrity Team
Dell, Inc.
Aubrey_Sparkman@Dell.com
(512) 723-3592

-----Original Message-----
From: Tom Dagostino [mailto:tom@teraspeed.com]
Sent: Tuesday, October 12, 2004 11:03 PM
To: Sparkman, Aubrey; nitin.bhagwath@hp.com; rlecona@siu.buap.mx;
ibis-info@eda.org; ibis-users@eda.org
Subject: RE: [IBIS-Users] V-t curves offset

Well, not really true.

Say for instance you have a buffer that has a 1 nsec rise and fall and
the delay in the buffer is 20 nsec before the edge occurs (I've seen
worse in real models). Now lets try to make this toggle. Apply a 100
MHz input frequency to the buffer. It will try to make a positive
transition. But it will have to wait 20 nsec before this can happen.
But at 10 nsec the input has decided that now it wants to go negative.
In this example the buffer will never toggle.

In a properly constructed output model the delay is minimal and the
delay is proper for both the rising and falling waveforms. The min, typ
and max VT curves will likely have different delays with the max the
least amount of delay.

Many simulators now have features that will strip out common delay in
the rising and falling VT curves but this may have the affect of
removing any asymmetry the buffer may impose on a 50% duty cycle
stimulus.

Tom Dagostino
Teraspeed Consulting Group LLC
503-430-1065
tom@teraspeed.com
www.teraspeed.com

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Aubrey_Sparkman@dell.com
Sent: Tuesday, October 12, 2004 6:54 PM
To: nitin.bhagwath@hp.com; rlecona@siu.buap.mx; ibis-info@eda.org;
ibis-users@eda.org
Subject: RE: [IBIS-Users] V-t curves offset

Nitin,
I think you are correct; the delay of an IBIS buffer isn't relevant.

Ramiro,
If you are testing the IBIS buffer in HSPICE, try adjusting the delay of
the input stimulus to get the output waveforms aligned.

Aubrey Sparkman
Enterprise Engineering Signal Integrity Team Dell, Inc.
Aubrey_Sparkman@Dell.com
(512) 723-3592

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Bhagwath, Nitin
Sent: Tuesday, October 12, 2004 8:22 PM
To: RODRIGUEZ_LECONA_RAMIRO; ibis-info@eda.org; ibis-users@eda.org
Subject: RE: [IBIS-Users] V-t curves offset

Hi Ramiro,

Ibis models are one port models, and so do not have a concept of
input-to-output delays. So you can't really compare a transition time
from a two port Spice model with a one port Ibis model which might use a
stimulus to generate its output waveform.

If this has changed, or is being planned to change, I would be most
interested in finding out (and using!).

Regards
-Nitin

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of RODRIGUEZ_LECONA_RAMIRO
Sent: Tuesday, October 12, 2004 5:36 PM
To: ibis-info@eda.org; ibis-users@eda.org
Subject: [IBIS-Users] V-t curves offset

Hi all,

I'm working with IBIS models validation and I have a problem
correlating the IBIS model with transistor level buffer in HSPICE. I
simulate both buffers with the same conditions (same load, temperature,
voltage supply) and the rising/falling edges of the outputs are equal
but there is a delay between IBIS model output waveform and transistor
level

buffer output waveform. I shift the V-t Tables in the IBIS model to
compensate the delay and the output waveforms are matched but this
occurs when the input signal has rising/falling times equal to the
rising/falling times used to extract the IBIS model, if I use a input
signal with rising/falling times lower than the rising/falling times
used to extract the V-t curves then the buffer implemented with the IBIS
model has again a delay.
   What happens?
   How can I understand this? How can I avoid this delay?
   Or this phenomenom is normal because the important thing is the edge
waveform (buffer switching behavior) and the delay obtained is not
relevant?
   Or the V-t curves obtained with specyfic rise/fall times are only
valid to simulate buffers with input signals with the same rise/fall
times ?

Thanks.

Regards.

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