[IBIS-Users] Re: Basic questions about IBIS

Andrew,

Gee, I was hoping some others would chime in here by now. Oh well.

> About 3,
> A. So, chips are usually not made according to SPICE file;
> On the contrary, SPICE files are extracted from chip and guess.

Essentially yes, but early SPICE files can also be created before a chip is
designed, based on the schematic for the chip, and on the designer's
expectations. You can make SPICE files from either a schematic design, or
an actual chip layout.

When someone is designing a chip, they can make SPICE files that represent
how they hope the chip will behave, before there is any silicon or even a
layout. If it is a new IC process too, then you could say the entire SPICE
model including its .MODEL parameters includes some guess, since even the
process has not been proven yet.

After the chip is made, they can also make SPICE files that represent the
final, actual chip layout. Not everyone goes through both steps.

In any event, a good IC designer *should* always adjust their final SPICE
models (whether they came from schematics or from the layout) according to
how the chip actually behaves. Usually not the other way around. It is
easier to make a SPICE model fit actual silicon behavior, than the other way
around.

If the chip doesn't behave the way he wanted it to, he may go back and tweak
the chip design somewhat, but in the end, he ought to adjust the SPICE model
according to how the chip truly behaves.

> Thus, SPICE-derived IBIS model and encrypted SPICE
> model are not as accurate as measurement-based IBIS model. (except some
> situation)

SPICE models, whether encrypted or not, could be just as accurate as any
IBIS model. (Encryption has nothing to do with it.)

On basic principles, a SPICE-derived IBIS model could be less accurate than
a measurement-based IBIS model, because it is one more level removed from
reality. Each level, or translation from one form to another, incurs
additional errors.

Reality is the chip itself. A SPICE model that has been correlated to agree
with measurements, is one level away from reality. An IBIS model from
measurements, is also one level away from reality. An IBIS model created
from the SPICE model, is two levels away from reality, so there CAN be a
greater chance of it not agreeing with reality. But it's not a guarantee.

A SPICE model that has never been correlated with measurements, should be
treated with suspicion, and an IBIS model derived from it is almost surely
less accurate than one made from measurements.

But on the other hand, anyone can create a lousy IBIS file from
measurements.

If someone hands you a chip and a SPICE model, and asks you to make an IBIS
model, you may not know who created the SPICE model and whether it is
accurate. There are many bad SPICE models out there too. Making a SPICE-
derived IBIS model could just perpetuate a lie that was in the SPICE model,
that the designer never bothered to correct. Making a measurement-based
IBIS model can at least be traced to the chip's actual electrical behavior.

> B. So, the extremes of SPICE-derived model are only
> expectations. ...

I'm not in the IC process business so I don't "know the real scoop" here ...
but as far as process extremes is concerned, I believe that the following
are true:

(1) IC manufacturers set statistical limits on their IC process, beyond
which there is some statistical confidence that no (defect-free) parts will
be made. Some SPICE model extremes are based on these statistical
expectations.

IC vendors can also make test chips that are meant to represent the process
extremes, which they do by intentionally varying some key factor(s) in the
chip-making process. Because they require special changes to the IC
process, they aren't cheap. In theory they can use these test chips to
verify SPICE model extremes.

(2) IC manufacturers put test limits into their automatic test equipment,
used to test and screen every part manufactured, and this tends to set the
limits on the extremes of characteristics of the parts they sell. (Except
for black-market (reject) parts that sometimes find their way onto the
market!) Because the ATE tests may or may not directly test the parameters
of interest, sometimes they are indirect.

> C. If everything is optimized, how long will it usually
> take to generate a IBIS3.2 model of one I/O buffer?

Gee, I don't know ... I'm going to guess no more than a day? (Maybe two;
one to measure, one to massage the data.) Assuming of course that the
people doing it were really set up beforehand and didn't need to do any more
research or fixturing, and that the package modeling is simple.

> About 4,
> A. I would like to know whether the influence from fab process
> is smaller than the influence from temperature and voltage or not.

This is probably a moving target, and it's been a while since I looked at
this, but I recall that the fab process was dominant. Today they may have
tighter controls on process variations, which might have reversed that.

They can also design temperature and voltage compensated buffers that remove
some of those dependencies on (say) buffer speed.

> B. For most IBIS model, the typical temperature is room
> temperature, however, for some chips (ex: CPU), the temperature is much
> higher than room temperature.
> Is it reasonable to ask chip vendors to change the
> typical temperature.

That's a really good thing to discuss with whoever makes your IBIS models.
It's one of the things I don't particularly like about models that include
environmental effects. No chip runs at room temperature.

> 5. In IBIS, the "max" curves are measured / simulated under the condition
> "maximum buffer strength + lowest temperature + largest voltage"
> and the "min" curves are measured / simulated under the condition
> "minimum buffer strength + highest temperature + smallest voltage".
> I think it is not sufficient to simulate the ringback: as I know the
> ringing caused by maximum buffer strength is much larger the minimum
> buffer strength, but "smallest voltage - VIH" is smaller than "largest
> voltage - VIH", we cannot make sure whether the ringback margin is
> sufficient even if the simulation results of min and max passed. (Because
> the smallest ringback margin should be under the condition "maximum buffer
> strength + lowest temperature + smallest voltage")

I think this question deals more with the particular simulation strategy
(and the simulator) you use.

You could simulate using a "max" model for the driver and a "min" model for
the receiver, if your simulator allows you to do this. (Unless, of course,
you are talking about a bi-directional transceiver monitoring its own
output.)

Personally, I prefer to decide what input thresholds *I* want to use, so in
SPICE I look for the worst-case input thresholds, plus a small margin, and I
ignore what the IBIS model may say.

I hoped someone else would comment on that question.

> 6. Chip vendors usually set the largest and smallest voltage according to
> their maximum tolerance (for example 20%), however, the voltage error rate
> of our regulator is usually not so large. So the worst cases in IBIS
> model are not the same with the worst cases in our PCBA. Furthermore,
> sometimes the typical voltage we use is not the same with the original. I
> would like to know whether there is a method to generate the IBIS model we
> need.

I don't know. Except that you could have someone create custom IBIS models
for your particular needs.

You have cited many of the reasons why I prefer to use SPICE models rather
than IBIS models! In recent years I have been rather disappointed to see so
many IBIS models *replace* SPICE models in terms of their availability. To
me, nothing beats a good SPICE model. A good SPICE model does what you want
it to. An IBIS model doesn't. But it keeps the lawyers happy. :-(

Regards,
Andy

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Received on Mon Jan 10 08:03:17 2005