RE: [IBIS-Users] Capacitance and transition time

Sorry for the late reply, but things were a bit hectic.
However, this is an important question and I would like
to reply to it.

Unfortunately I need to disagree with the previous replies.

I have seen several cases when IBIS models do not perform
well with capacitive loads.  Especially when the capacitive
load comes as a series DC blocking (decoupling) capacitance
placed in the path of the signal.

Searching for the reasons, I realized that this may be
inherent in the basic 2-equations 2-unknowns algorithm
(most) tools may be using(?).  (I don't know for fact
what the algorithms of various tools are, so I can't
answer that question).  This algorithm uses Kirchoff's
and Ohm's law to convert the V-t curves into k-t curves
which are ultimately used to scale the static I-V curves
in the model.  The problem with this is that the equations
of reactive loads (C and L) include dV/dt and dI/dt, which
is missing from this algorithm all together.

Now, if the circuit is such that the dI/dt and dV/dt 
components are small with respect to the Ohm's law
relations, you will see relatively accurate results.
However, if the reactive elements dominate the voltage
and current relationships, chances are that your
simulation results will not be very accurate.

Interestingly, T-line loads do not fall into the category
of reactive loads, they look very much like resistive
loads, so we do not need to be worried about those.

I will have a short presentation on this in the upcoming
IBIS Summit meeting, which will be uploaded to the IBIS
web site shortly.  This will be more like a problem
statement only, but I hope that this will put things
in perspective.

Arpad
----------------------------------------------------------


-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf Of Hazem Mahmoud Hegazy
Sent: Tuesday, January 31, 2006 1:25 AM
To: IBIS-USERS
Subject: Re: [IBIS-Users] Capacitance and transition time

I agree with Tom that IBIS will produce very good resluts 
on different capacitive loads. In some cases, usually LVDS 
drivers(due to their high sensitivity to even resistive 
load), we might face a problem but not very likely.
BR,
Hazem



On Mon, 30 Jan 2006 22:50:21 -0500
  "Andrew Ingraham" <a.ingraham@ieee.org> wrote:
>In normal usage, the actual load (i.e., traces and other 
>devices) connected
>to an output device creates a rather complex, frequency 
>dependent load.
>It's highly unlikely that the output device was 
>characterized with that kind
>of load.
>
>While there may not be a guarantee, one should expect 
>that an IBIS model
>would produce reasonably good results with such complex 
>loads as well as
>simple R/C loads (with not unreasonable values), even 
>though they weren't
>use to generate the VT curves.
>
>Anyway, most VT curves are established with resistive 
>loads (zero
>capacitance), which "never" happens in practice.  The VT 
>curves may be used
>only to "calibrate" the simulator's representation of the 
>ouput device, not
>to generate actual waveforms.
>
>Regards,
>Andy
>
>
>> A coworker wants to simulate what affect connecting
>> different capacitors to the output pin of a device
>> would have on its transtion time.  He doesn't have
>> access to spice models and he asked me if he could use
>> IBIS models.  I told him that since the models are
>> characterized under a given load, changing that load
>> in simulation may not give him very accurate results.
>> Was I correct, or will the simulator use the values of
>> the IV curves and test fixture to accurately skew the
>> rise and fall times specified in the VT curves?
>
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