Re: 3D, or I/V/T models

Hi Arpad,

This is my understanding of your statement of the problem. See if
it helps.

> Hello IBIS folks,
>
> On your request, here is a little summary on the 3D or I/V/T
> representation of buffers.
>
> To simplify the following discussion I will only consider the
> pulldown part of an output buffer, which is nothing but an Open-Drain
> output. In this case the Drain of the transistor is connected to the
> output of the buffer, the Source is connected to GND, and the Gate is
> driven by the pre-driver circuitry.
>
> With the current V/I curve approach we only characterize the DC steady
> state conditions of the transistor after it has been completely
> turned on. This means that when we sweep the Drain of the transistor
> to obtain a V/I curve, its gate voltage is at maximum (5V).
>
> If we want to characterize the switching characteristics of the
> transistor while it is being turned on (i.e. while its gate voltage
> is transitioning from 0V to 5V), we would have to take a family of
> V/I curves at various gate voltages. There is nothing new in this
> idea, most transistor data books publish such family of curves for
> both FETs and BJTs. Our problem is that it is very difficult or
> impossible to access the voltage waveform on the gate of an output
> transistor.

Is the difficulty with actual physical measurement such that you cannot
probe the input node of the gate? Then how about in spice simulation? I
can thinks of a method like this: use the Vds/Ids/Vgs family of curves
and Vgs/Time of the input voltage. Mapping Vgs from the curve 1 to Vgs
in curve 2, then you can arrive at a Vds/Ids/Time surface.

Mathematically, curve 1 is Ids = f(Vds, Vgs)
                curve 2 is Vgs = g(time)
combining both, Ids = f(Vds, g(time))

In physical measurement, curve 1 can be obtained by slowly sweep I/V curve
of the output by setting input voltage to a set of fixed values. The only
limitation is: you cannot isolate either the pull-up or pull-down. In IBIS
[pull-up] and [pull-down] voltage specifications are different. Curve 2
can be obtain by probing the input node voltage get a waveform by an
oscilloscope.

>
> However, we can look at the output current on the Drain as a function
> of two variables which are the Gate-Source and the Drain-source
> voltages. By the superposition principle, to measure the effects of
> the Gate-Source voltage on the output current we can keep the
> Drain-Source voltage constant, and to measure the effects of the
> Drain-Source voltage we can keep the Gate-Source voltage constant.
>
> In practice, this means that I can measure the output current of a
> transistor with respect to time while keeping the output voltage at a
> constant level (short circuit into a given voltage) to get the
> switching characteristics of the transistor (i.e. the effect of the
> Gate-Source voltage waveform with respect to time). The present V/I
> measurement method takes care of the other variable, namely the
> Drain-Source voltage at a constant Gate-Source voltage, since the
> transistor is in a fully turned on steady state with the Gate-Source
> voltage being a constant 5V when we sweep it.
>
> If we plot the data measured this way, we can actually generate a 3D
> surface-plot. The two horizontal axis represent the independent
> variables, one of them being time, and the other the output voltage
> (Drain-Source voltage). The vertical axis represents the dependent
> variable, the output current. This is where the name comes from: 3D
> or I/V/T model.
>
> The nice part of this approach is that the device under test does not
> have to be a MOSFET transistor. In fact, it can be anything and we
> can treat it as a black box. The surface plot will still fully
> describe its characteristics.
>
I think this may not be as device independent as first appear. In the
analysis, the MOS is working in a common-source mode. Source current
is a function of (gate-source, drain-source) so that change of drain
voltage only affect one variable: the drain-source voltage. In
common-emmiter mode, as in ECL output stage, collector current is a
function of (base-emitter, collector-emitter) so change of emitter
voltage affect both variables.

> The only difficult part is that we must have a current meter that is
> extremely fast. There could be several hundred milliamp changes in a
> couple of nanoseconds. Such current changes are very susceptible to
> parasitic inductances, therefore a careful measurement methodology
> must be worked out to obtain correct data.

This will be a concern for company which does not the kind resources
Intel has. Further more, mixing DC and AC parameters in your calculation
means you have to take into account all reactive elements and high
frequency effects.
>
> With the widespread use of the various kinds of slew rate controlled
> buffers in the industry, there is an urgent need to find an accurate
> modeling method for the switching characteristics. The 3D or I/V/T
> characterization method could be useful for more accurate modeling of
> traditional buffers as well as slew rate buffers without turning back
> to transistor level models.

I am confused about the purpose of the [RAMP] data in the ibis file. I
think its purpose is to construct the waveform of the sending end before
any reflection arrives. Does it mean that with the I/V/T characterization
method, [RAMP] information is no longer required.
>
> I would be glad to hear your comments and suggestions.
>
> Sincerely
> Arpad Muranyi
> Intel, Coprporation
>

Best Regards,

Siuki Chan
Logic Modeling Corp.
Received on Wed Sep 22 10:45:36 1993