BIRD for ECL

                 Buffer Issue Resolution Document (BIRD)

BIRD ID#: 0001
ISSUE TITLE: ECL Extensions
REQUESTER: Stephen Peters, Intel Corp.

DATE SUBMITTED: September 22, 1993
DATE ACCEPTED BY IBIS OPEN FORUM:

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STATEMENT OF THE ISSUE: This proposal addresses the need to extend the
IBIS specification to include devices with Emitter Coupled Logic (ECL)
type output structures.

The proposed changes are three in number:
     (1) Adding one more choice to the [Model] keyword sub-parameter
         'Model_type'
     (2) Lessening the required voltage range over which an ECL output
         is characterized
     (3) Explicitly specifying under what output conditions data is
         gathered for inclusion in the pullup and pulldown tables

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

(1) The first change is to add the choice of 'ECL' to the list of allowed
choices for the 'Model_type' sub-parameter used with the [Model] keyword.
This choice must be used when the device output being described has an
ECL type output structure. Specifically, change the description of the
[Model] keyword as follows:

WAS:
  [Model] model_name
  Model_type Input, Output, I/O, 3-state, Open_drain | List only one
        .
        .
        .

PROPOSED:
  [Model] model_name
  Model_type Input, Output, I/O, 3-state, Open_drain, ECL | list only one
        .
        .
        .

(2) The second change is to relax (decrease ) the range of voltage values
required when tabulating the V-I characteristics of an ECL output. For an
ECL device it is proposed the range be decreased to VCC (the most positive
power supply) to VCC - 2.2 volts (currently the range is from GND - POWER
to 2*POWER). Specifically, add the following to Item 2 in the "NOTES ON
DATA DERIVATION METHOD" section of the specification:

     When tabulating output data for ECL type devices, the voltage points
     must span the range of VCC to VCC - 2.2V. This range applies to both the
     pullup and pulldown tables. Note that this range applies ONLY when
     characterizing an ECL output.

(3) Finally, it is proposed to explicitly state in the specification under
what output conditions data is gathered for the pullup and pulldown tables
and that, in both cases, the voltage data is referenced to VCC. The
proposed explanation should be placed in the 'Other Notes' section of the
text describing the [Pulldown] and [Pullup] keywords and is as follows:

     When tabulating data for ECL devices, the data in the pulldown table
     is measured with the output in the 'logic low' state. In other words,
     the data in the table represents the V-I characteristics of the
     output when the output is at the most negative of its two logic
     levels. Likewise, the data in the pullup table is measured with the
     output in the 'logic one' state and represents the V-I characteristics
     when the output is at the most positive logic level. Note that in BOTH
     these cases the data is referenced to the VCC supply voltage, using
     the equation Vtable = Vcc - Voutput.

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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

     In the following discussion I am assuming the reader understands
the basic operation of an ECL logic gate and the emitter follower output
structure. I am also defining VCC to be the most positive supply, while
GND as the most negative supply. A "totem-pole" output is the standard
type output structure with the source (emitter) of a pullup transistor
connected to the drain (collector) of a pulldown transistor.

(1) The purpose in requiring the user to specify 'ECL' in the Model_type
sub-parameter is to give a simulator an explicit indication that the device
being modeled has an ECL type output structure. As far as the IBIS spec
is concerned, the fundamental difference between an ECL output and the
standard totem-pole or open-drain/collector output is that, for ECL, data
in the PULLDOWN table is referenced to VCC and changes in VCC effect the
logic low voltage output level. This means when simulating an ECL output a
simulator must construct a different model and make different assumptions
regarding the output characteristics of the device. The following
discussion explains these differences in more detail.
     Currently, voltage data points in the pulldown table are referenced
to GND. This is because in a standard totem-pole type output the output
voltage in the logic low state is determined by Vds (or Vce) of the
pulldown transistor, and the source (emitter) of this transistor is tied
to ground. However, in ECL type outputs the output voltage in the logic
low state is determined by the voltage at the base of the output emitter
follower, and this voltage is with respect to VCC, not GND. As a specific
example, it does not matter whether VCC is defined as 0v or 5v, the output
voltage of an ECL gate in the low state is always going to be about 1.7v
below the VCC supply. By the same reasoning, a shift in VCC with respect
to the other supply will not change the logic low output voltage of a
totem-pole output but it will change the logic low level of an ECL type
output.
     Because the simulator cannot, apriori, determine the proper output
model (totem-pole or ECL) some indication of the output type is required.
One could argue that the simulator could inspect the data in both
tables and assume that if the range was 0 to -2.5 it was dealing with an
ECL type output, however, I don't believe this is (a) reliable (can we
GUARANTEE that no other device will be specified with those voltage ranges)
and (b) the IBIS specification should place specific implementation
requirements on a simulator. Therefore, the easiest and most reliable
way to explicitly specify the output type is with the Model_type
sub-parameter.

(2) The reason the voltage range over which an ECL output is specified
should be relaxed is that, with ECL, one is dealing with much smaller
signal swings and terminated transmission lines.
     The rational for specifying such a large voltage range was to allow
for the case of a CMOS output driving an unterminated transmission line.
When an incident voltage wave hits the end of an unterminated line it
will reflect back to the source at double the amplitude. Thus, a CMOS
output that swings rail-to-rail could see a reflection of up to 2*VCC
(or -VCC in the negative direction). However, with an ECL output, the
output swing is only ~800mv (typically -.9v to -1.7v) and furthermore,
because of the vary nature of ECL, any transmission lines will be
terminated with an Rt close to the lines Zo. Even in the case where the
mismatch between Zo and Rt is 2:1, the maximum reflection is .270mv,
and the voltage range at the source due to reflections is -.6 to -2.0v.
Therefore, a range of VCC to VCC -2.2v is adequate to specify the output
under any reasonable conditions, and should be enough to allow simulators
to extrapolate the curves. Note also that there are no gnd or power clamp
diodes on ECL outputs (or inputs for that matter) and so those are
'don't care' issues.

(3) The third proposal is an effort to make perfectly clear to both the
user and the person creating an IBIS specification for a particular part
how ECL device are to be handled.

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ANY OTHER BACKGROUND INFORMATION:

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Received on Wed Sep 22 17:03:34 1993