Some more yet on the power bus question

Hi, ibis folks -
Thus saith bracken@valhalla.performance.com on 12 DEC 93 at 1538.48 hrs :
>
>Bob,
>
> I have a few questions regarding this "complex" example:
>
> 1) You say "in at least one case" this will occur--that makes it sound
> like you folks don't design things this way very often. Do you
> see that situation changing (i.e. will more designs be done this
> way in the forseeable future?)
>
> 2) How fast is such a design operating? The faster you go, the more
> important the "details" become.
>
> If it's a high-speed design that needs a high level of detail, then it
> seems to me that you have the following choices:
>
> a) Use a SPICE subcircuit, with elements for each "leg" of this
> topology;
>
> b) Measure the Z-parameters of the structure (inject an AC current
> into each pin, and measure the resulting voltage drops
> to every other pin.) Do this versus frequency from DC
> to "daylight" (or the maximum freq. of interest.) Or, use S
> parameters.
>
> c) Use RLGC matrices, with some additional information about how
> each "leg" comes together at various nodes. I assert that
> this approach is tantamount to having a SPICE subcircuit,
> but harder to read.
>
>You're quite right that the laboratory measurements become very
>difficult, even for finding the S or Z parameters. For SPICE or RLGC
>matrices, lab work may be next to impossible. At that point, you need
>numerical field solver software to generate the equivalent RL(G)C
>networks.
>

We have just started this style of grouping with some faster parts in hopes
of getting less interaction between simultaneously switching drivers. The
proof is in the testing, and if it works well, we will do more parts this
way. Just at the moment we have done a couple that are not yet publically
announced, but are fast. The details are indeed important. I will not
upstage the announcement by saying just how fast is fast, but "Spice level"
simulations show the sensitivity to detail to be considerable. I would hope
to be able to make ibis style models rather than Spice models for all the
usual reasons, less work ( maybe ), less exposure of proprietary circuitry,
etc. The use of RLGC matrices was kicked around at the summit, and may be
the only real option for this case. In fact it may be the primary option for
capturing leadframe parasitics in general.

I would, as I assume most of us would, like to see a more "ibis-like"
description, but that may not be possible. I am awaiting a paper from one of
our modelling labs here concerning measurement of package parasitics to see
if the methods they discuss are applicable here. I am told that I can share
at least a summary, if not the whole paper, with the ibis group, and I will
as soon as I receive it and make a little sense out of it. Real heavy duty
field solving will probably become necessary before much longer to get a good
representation of package parasitics, since measurements are very delicate at
best.

The main thrust of what I am saying in my example is that "here are shades of
things to come" and I hope we can grow ibis into a big enough and tough
enough bird to be able to handle it.

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     __ /
    / \ / / Bob Ward
   /__ / / / / / / MSG: SQU
  / \ _ /_ / / / _ __ _ / INET: bward@dadhb1.ti.com
 (____ / (_)_ /__) (__(__/ (_(_/ (_(_/ 713+274-4146 Voice
                                                      713+274-3911 Fax

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                                  (o o)
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        Here I sit in endless joy, 'cause I was here before Kilroy!!!
Received on Thu Dec 2 13:46:08 1993