Re[2]: Hi frequency stuff

Dear Ravender (and all IBISers),

I am not sure if I don't understand what you are talking about or
whether you missed something in the IBIS spec.

Currently, we have C_comp and C_pkg defined in IBIS. Schematically it
can be drawn like this:

  +------+
  | |
  |Buffer|------+--L_pkg----R_pkg--+--o Output
  | | | |
  +------+ ===C_comp ===C_pkg
                | |
               GND GND

This picture can be mirrored for an input structure. What you describe
below as Collector to Emitter (or Source to Drain) capacitance looks to
me as C_comp and C_pkg is there for the (lumped) packaging capacitance.
I think what you are asking for is already there.

Arpad Muranyi
Intel Corporation
Folsom, CA

        Reply to: RE>>Hi frequency stuff
I agree in the case of driver pin, the input- cap will be effective
only if the predriver is defined as non- ideal source. However, for the
driver pin the output capacitor (collector to emitter or drain to
source) with- in the black box may be important. Also, how about the
receiver pin, where the pin is driven by the interconnect impedance? In
this case (receiver pin) the impedance match or mismatch between the
interconnect and pin will be important and may not need to define
preamplifier.... Thanks......

Ravender
--------------------------------------
Date: 1/7/94 9:42 AM
To: Ravender Goyal
From: Arpad Muranyi
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Date: Fri, 7 Jan 94 09:38:06 PST
From: Arpad Muranyi <Arpad_Muranyi@ccm.hf.intel.com>
Message-Id: <940107093806_6@ccm.hf.intel.com>
To: ibis@vhdl.org
Subject: Re: Hi frequency stuff

Hi IBIS folks,

To respond to this (Hi Frequency) issue, it seems to me that those
capacitors on the input side of the "Black BOX" do nothing if the
buffer is driven with an ideal source (zero impedance). This might
be the case in some IBIS implementations. Those capacitors will have
a correct effect only if the predriver is modeled correctly.

Are we ready to add more V/I curves to the IBIS standard to describe
the predriver?

Arpad Muranyi
Intel Corporation
Folsom, CA

Sorry, in my last message, it seems that the figures did not come
through
-good.
Let me make another attempt here.

Ravender
------------------------------------------------------------------------------
-
-

--
I am starting this discussion to get your inputs on including the high
frequency effects  (4- 5 GHz) in IBIS models.
As we know the signal integrity analysis accuracy depends as much on
accurately evaluating the electrical characterisitcs (characteristic
impedance, trace velocity, dispersion, to name a few) of interconnects,
as it depends on the accuracy of evaluating or specifying the
terminating impedances- i.e. the i/o models.
For EMI (Electromagnetic Interference) analysis, the frequency of
analysis is upto several GHz, as required by the FCC, European FCC etc.
guidelines. Hence, for EMI analysis upto what ever frequency of
interest, it is critical to have  i/o model that is valid at that
frequency, else results from EMI analysis could be grossly  inaccurate.
In order to include the high frequency effects, it is general
impression (as I have heard in the past) that one may have to give up
the proprietary information about the process. However, just for
accurate impedance presentation, that may not be necessary. To give an
example:
1- Today the i/o model is represented as follows:
                 o Vcc/ Vdd etc.
                 |
                 |
                 |
            _____|_____
           |     B     |
           |     L     |
           |     A     |
           |     C     |
   o-------|     K     |------o output
 input     |           |    |
           |     B     |    |
           |     O     |    |
           |_____X_____|   === pin capacitance
                 |          |
                 |          |
                 |-----------
                 |
                 o
               Ground
The black box today is an i/v curve which results in a real impedance
only. The  imaginary part of the impedance is contributed by the pin
parasitics only. We all know that the semiconductor devices have
capcitance that will also contribute to the imaginary part of the
impedance.
2- At higher frequencies (5- 6 GHz), the device capacitances can be
accounted for, as a first order approximation, as follows:
                 o Vcc/ Vdd etc.
                 |
       ----------|
       |         |
       |    _____|_____
       |   |     B     |
      ===  |     L     |
       |   |     A     |
       |   |     C     |
   o-------|     K     |------o output
 input |   |           |    |
       |   |     B     |    |
       |   |     O     |    |
       |   |_____X_____|   === pin capacitance
      ===        |          |
       |         |          |
       ----------|-----------
                 |
                 o
               Ground
There may be another feedback capacitance from supply to ground. How
these capcitances can be estimated, or measured are to be addressed.
Also, what will be the optimum model to include the device
capacitances, needs to be discussed.
However, the primary question to address is, are these effects
important to take into account for signal integrity/ EMI analysis?
Secondly, is it within IBIS's charter to address such effects in the
models?
Thanks & look forward to hear from fellow IBISians......
Ravender