Re: Re[2]: GND Plane Bounce Question

Samie,

I agree. However, it is not a matter of where you measure.
As soon as your prober touches the bit of interest, SSO noise will
be reduced because of the current through the prober capacitor
to the ground plane. In that case, true Tco will be in question.

Regards,

Sung Oh
VLSI Technology, Inc.
 
>>From Samie_Samaan@ccm2.jf.intel.com Tue Aug 22 09:11 MST 1995
>>Date: Tue, 22 Aug 95 08:43:00 PDT
>>From: Samie Samaan <Samie_Samaan@ccm2.jf.intel.com>
>>To: ibis@vhdl.org, fyuan%qdt.com%uunet@uunet.uu.net,
>> uunet!uunet!ccm2.jf.intel.com!Samie_Samaan@uunet.uu.net
>>Cc: uunet!qdt.com!jonp@uunet.uu.net, uunet!qdt.com!fyuan@uunet.uu.net
>>Subject: Re[2]: GND Plane Bounce Question
>>Content-Type >>: >>text >>
>>Content-Length: 7935
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>>
>>
>>Text item:
>>
>> Frank,
>>
>> Thank you very much for taking the time to address this problem. In
>> fact I would like to know more about this tool, if you can send me
>> some info on it. My address is with Quad, and also at the bottom. The
>> numbers you give me are a big help. With a formula provided by someone
>> else, I will have a good idea of what to expect.
>>
>>
>> I would like to comment on this whole issue a bit, and address what
>> prompted my question in the first place:-
>>
>> Some of the colleagues who answered my inquiry, correctly indicated
>> that I should designate the source of the current and not just its
>> sink. So I answered one of them by saying the following: Assume that I
>> can magically inject the current into the GND plane thru the
>> via...etc. The reason I say that is because I was really interested in
>> local bounce, with the closest discontinuity to the GND plane being a
>> few inches away. Such a case arises when you are dealing with, say,
>> open collector buffers, where the collector is tied to a signal trace
>> on the top layer of my hypothetical board, while the emitter pumps the
>> GND plane thru the via. The source of the current has to tie back to
>> the plane at some distant point, but that is not very relevant (in my
>> opinion) during the first few 100 ps's of the transient around the
>> via.
>>
>> The real reason I asked the above question has not been stated by me
>> yet. Well, here it goes: If one is trying to measure Clk-out delay
>> (Tco) of a buffer using a scope, and places the scope ground near my
>> via, while placing the scope's active lead at the bit of interest,
>> then, I believe, that if many bits are switching, that the waveform
>> seen by the scope would be distorted by the GND plane bounce. Say you
>> have a falling edge (while many bits toggle down), then since the GND
>> bounces up, the scope would read a smaller voltage (its gnd lead is
>> moving up too), and show the edge to be just as fast as when a single
>> bit switches (or nearly so) even though the edge has --in reality--
>> slowed down due to SSO. So one has to be more clever as to where to
>> measure Tco is such situations.
>>
>> Do others agree with my assesment ??
>>
>> Sincerely,
>>
>> Samie Samaan
>> Intel
>> 2111 NE 25th Ave
>> Hillsboro, OR 97124.
Received on Tue Aug 22 13:44:18 1995