Text item:
Frank,
Thank you very much for taking the time to address this problem. In
fact I would like to know more about this tool, if you can send me
some info on it. My address is with Quad, and also at the bottom. The
numbers you give me are a big help. With a formula provided by someone
else, I will have a good idea of what to expect.
I would like to comment on this whole issue a bit, and address what
prompted my question in the first place:-
Some of the colleagues who answered my inquiry, correctly indicated
that I should designate the source of the current and not just its
sink. So I answered one of them by saying the following: Assume that I
can magically inject the current into the GND plane thru the
via...etc. The reason I say that is because I was really interested in
local bounce, with the closest discontinuity to the GND plane being a
few inches away. Such a case arises when you are dealing with, say,
open collector buffers, where the collector is tied to a signal trace
on the top layer of my hypothetical board, while the emitter pumps the
GND plane thru the via. The source of the current has to tie back to
the plane at some distant point, but that is not very relevant (in my
opinion) during the first few 100 ps's of the transient around the
via.
The real reason I asked the above question has not been stated by me
yet. Well, here it goes: If one is trying to measure Clk-out delay
(Tco) of a buffer using a scope, and places the scope ground near my
via, while placing the scope's active lead at the bit of interest,
then, I believe, that if many bits are switching, that the waveform
seen by the scope would be distorted by the GND plane bounce. Say you
have a falling edge (while many bits toggle down), then since the GND
bounces up, the scope would read a smaller voltage (its gnd lead is
moving up too), and show the edge to be just as fast as when a single
bit switches (or nearly so) even though the edge has --in reality--
slowed down due to SSO. So one has to be more clever as to where to
measure Tco is such situations.
Do others agree with my assesment ??
Sincerely,
Samie Samaan
Intel
2111 NE 25th Ave
Hillsboro, OR 97124.
______________________________ Reply Separator _________________________________
Subject: Re: GND Plane Bounce Question
Author: fyuan%qdt.com%uunet@uunet.uu.net at SMTPGATE
Date: 8/21/95 6:31 PM
Hi, Samie,
I did some quick and simple simulations for your GND plane bounce problem
using the power/ground plane simulation tool we have at Quad Design.
The PCB is same as yours, and the size is 10x10 inch. Assume the current
is 10 mA (instead of 10 Amps in your message), and there are no de-caps or
other loads between the power/ground plane, the local ground bound is about
8 ~ 10 mV, assuming the current source has a 50 ohm internal resistance.
The ground noise propagates all over the plane, so the bounce away from the
via is lower but not too much than that at the vis. Depending on location,
the bounce is 2 ~ 6 mV. The location of the via also have some effects on
bounce, but is usually small.
Note that if you really have a 10 Amps current, the bounce would be 8 ~ 10
volts. That will be a truly unusual or extrame situation.
The above results assuming the power/ground planes are open (or no other
terminations), This usually gives higher estimate of GND bounce because of
the resonance of the plane. From my experice, the things affect the ground
bounce mostly are your loads, especially decoupling capacitors. Proper
placement of de-caps of 10~100 nf can significantly reduce the GND bounce
in the above situation, by 5 ~ 10 times. Resistive loads have little
effects on the GND bounce unless it is really small ( about 0.1 ohm for
the above example).
Our tool can do a much better job in extimating GND bounce if you have
more information about the geometry, the ternimation or load conditions,
and the source or device characteristics. Hope this is useful for you.
Regards
Frank Yuan
Quad Design Technology
(805) 988-8250
> From uunet!ccm2.jf.intel.com!Samie_Samaan Mon Aug 21 13:11:20 1995
> Date: Mon, 21 Aug 95 11:22:00 PDT
> From: Samie Samaan <uunet!ccm2.jf.intel.com!Samie_Samaan>
> To: uunet!vhdl.org!ibis
> Subject: GND Plane Bounce Question
> Content-Length: 1709
>
>
> Text item: Text_1
>
>
> All IBISians (SI experts by Default !!)
>
> I would like to pose the following SI question, and solicit help from
> those who actually know the answer or have a very good idea of how to
> estimate it by scaling from previous experience:
>
>
> Assume one GND and one power plane in a PCB separated by say 10 mil,
> with a dielectric constant of say 4. assume that the power plane has a
> via opening where current is injected thru the via down to the GND
> plane. Let's say that the current is 10 Amps. with a riserime of 1 ns.
> Assume nominal via diameter. The drawing below shows the structure:
>
>
> | Vcc
> ---------------- | ------------------
> | GND 10 mil, Er=4
> -----------------|-------------------
>
>
> What I would like to hear from anybody who actually has experienced
> GND plane bounce, is:
>
> *howmuch do you expect the GND plane (not the via stem) to bounce up
> (locally) given the above assumptions, and
>
> *howfar away from the via (radially) do you expect the bounce to drop
> to 10% of the peak which occurs right where the via meets the plane ?
>
> I would apprciate a good guess (and Why: perhaps from previous
> experience), or direction as to "who ?" you think could answer such a
> question. I know that I might need to do a 3-D or radial transmission
> line analysis of the system, but I'm really just looking for a quick
> answer.
>
>
> Thanks for taking the time to read or answer this question.
>
> Samie Samaan
> Intel Corp.
>
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Cc: uunet!qdt.com!jonp@uunet.uu.net, uunet!qdt.com!fyuan@uunet.uu.net
Subject: Re: GND Plane Bounce Question
To: uunet!uunet!ccm2.jf.intel.com!Samie_Samaan@uunet.uu.net
Message-Id: <9508220131.AA09604@hal.qdt.com>
From: uunet!qdt.com!fyuan@uunet.uu.net (Frank Yuan)
Date: Mon, 21 Aug 95 18:31:04 PDT
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