Fwd: [OVI/DC-TSC/WG-arch-No.22] Multiple Standards in Timing Verification

-- [ From: Ron Christopher * EMC.Ver #2.10P ] --

I should have addressed these concerns/questions to the IBIS forum as
well.
In hierarchical processing involving ASIC chips, I recommend there be
an IBIS model for each driver circuit and for each receiver circuit and
a standard representation for the physical parasitics. If this is
where we are going, then associating a single IBIS model with a
component MCM pin (if I understand IBIS) seems questionable for the
future?? My questions are illustrated in the referenced file.

Ron Christopher
------- FORWARD, Original message follows -------

> Date: Wednesday, 06-Sep-95 02:17 AM
>
> From: Ronald J Christoph \ Internet: (egjj77a@prodigy.com)
> To: Ron Christopher \ PRODIGY: (EGJJ77A)
>
> Subject: [OVI/DC-TSC/WG-arch-No.22] Multiple Standards in Timing
> Verification
>
> I have put some timing verification methodology and standards
concerns on
> the relationships between the DCL delay calculation language, IBIS,
and
> DIET into a framemaker .mif file. The file is timever.mif at
> ftp.cfi.org/incoming.
>
> I am sure it requires further explanation, or maybe someone has it
all
> resolved.
>
> Ron Christopher
>
>
>

------- FORWARD, End of original message -------
Received on Sun Sep 10 21:16:27 1995