Re: Stored Charge by Peivand Tehrani

Arpad,

I agree with you.
I believe what Peivand saw is a well-known Miller effect, which
is related to the gate to drain capacitance of the CMOS inverter.

Sung

>>From owner-ibis@vhdl.vhdl.org Tue Jul 23 11:03 MST 1996
>>Date: Tue, 23 Jul 96 10:34:00 PDT
>>From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
>>To: ibis@vhdl.org
>>Subject: Re: Stored Charge by Peivand Tehrani
>>
>>Peivand,
>>
>>I looked at your simulation example, and I think that you are referring to a
>>phenomena as the "glitch" which is unrelated to the "kickback effect",
commonly
>>associated with the charge storage effects (discussed in BIRD34) of clamping
>>diodes, ESD structures, etc.
>>
>>In my opinion the glitch you are observing is related to the parasitic
>>capacitances between Drain-Source, Gate-Source, and Gate-Drain. When the
gate
>>voltage of the inverter begins to switch, there is a time period when none of
>>the output transistors are (fully) on. The changing voltage on the gate
bleeds
>>through the parasitic capacitances to the output untill the transistor to be
>>turned on gets turned on. Since we are talking about an inverter, this
causes a
>>glitch that goes the opposite direction of the intended edge. If you try to
>>reproduce the same effect with a "voltage follower" circuit, you will see
that
>>the "glitch" will go in the same direction with the intended edge.
>>
>>Arpad Muranyi
>>Intel Corporation
 
>>==============================================================================
==
>>
>>
>>
>>Author: owner-ibis@vhdl.vhdl.org at SMTPGATE
>>Date: 7/19/96 5:50 PM
>>Priority: Normal
>>TO: bob@icx.com at SMTPGATE
>>CC: ibis@vhdl.org at SMTPGATE
>>BCC: Arpad Muranyi at FMCCM28
>>Subject: Stored Charge
>>------------------------------- Message Contents
-------------------------------
>>Hello IBIS fans,
>>
>> I was reviewing the stored charge BIRD 34.1 . I have observed the
>>same glitch effect even with ESD diodes removed. So I think this glitch
>>is not just created by the stored charge in the diodes. This glitch can
>>easily be observed with a simple CMOS invertor with a fast (100 psec)
>>ramp as the input of the invertor, I think this glitch is because of the
>>stored charge in the depletion region of upper and lower devices.
>>
>> I will send a simple SPICE file that I have been using to simulate this
>>effect. The SPICE version which I am using runs into convergence problems
>>if I remove Cd1 capacitor. This capacitor presents the die capacitor in
>>IBIS models. After the simulation the voltage at node 2 should be probed.
>>
>>Best Regards,
>>Peivand Tehrani.
>>
>>
>>**************************SPICE file************************
>>
>>
>>
>>Driver Device Transitions For Gate Transition
>>*************************************************************
>>VDD 3 0 5
>>*************************************************************
>>M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6
>>M2 2 1 3 3 QP L=1.5E-6 W=341E-6
>>*************************************************************
>>.MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 )
>>.MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200)
>>*************************************************************
>>VIN1 1 0 PULSE(5 0 0 .01n 0 100E-9 1E-3)
>>*************************************************************
>>Cd1 2 0 4p
>>R11 2 0 50
>>*************************************************************
>>.tran .001n 1n
>>.END
>>
Received on Tue Jul 23 11:30:17 1996