Re[2]: Stored Charge by Peivand Tehrani

Text item:

Sung, Peivand, and IBIS fans,

Here is a simulation example for what I wrote about in my previous EMAIL. I did
two things to Peivand's original simulation example:

1) Added a voltage-follower circuit, which is an N-channed pullup. A 50 Ohm
    resistor is connected between its output and GND. Observe nodes 10 and 20
    (Gate and Source).
2) Added a CAPOP parameter and a bunch of 0 values to turn of all (or most?)
    capacitance modeling that is given by HSPICE automatically.

(I am using HSPICE here).

To see the glitch with the non-inverting output, plot nodes 10 and 20. Notice
that the glitch goes in the same direction as the output is switching, that is,
rising edge output causes a positive glitch. (In Peivand's example the glitch
goes negative while the output is going positive). However, in both cases, the
glitches follow the direction of the input signal. This proves that the glitch
is related the input signal through parasitic capacitances.

To see that these glitches go away without parasitic capacitance, uncomment the
lines starting with "+ CAPOP ... " in both .MODEL statements. The glitches
should go away completely.

Arpad

Driver Device Transitions For Gate Transition
*************************************************************
.tran .001n 3.0n
.OPTIONS POST=1
VDD 3 0 DC=5.0V
*************************************************************
VIN1 1 0 PULSE (5 0 1.0ns 0.01ns 0.01ns 100E-9 1E-3)
M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6
M2 2 1 3 3 QP L=1.5E-6 W=341E-6
*Cd1 2 0 4p
R11 2 0 50
*-----------------------------------------------------------*
VIN10 10 0 PULSE (0 5 1.0ns 0.01ns 0.01ns 100E-9 1E-3)
M10 3 10 20 0 QN L=1.5E-6 W=136.4E-6
R10 20 0 50
*************************************************************
.MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 )
*+ CAPOP=0 CF1=0 CF2=0 CF3=0 CF4=0 CF5=0 CF6=0 CGBEX=0
.MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200)
*+ CAPOP=0 CF1=0 CF2=0 CF3=0 CF4=0 CF5=0 CF6=0 CGBEX=0
*************************************************************
*************************************************************
.END

----------------------------------------------------------------------
Arpad,

I agree with you.
I believe what Peivand saw is a well-known Miller effect, which
is related to the gate to drain capacitance of the CMOS inverter.

Sung
----------------------------------------------------------------------
>>Hello IBIS fans,
>>
>> I was reviewing the stored charge BIRD 34.1 . I have observed the
>>same glitch effect even with ESD diodes removed. So I think this glitch
>>is not just created by the stored charge in the diodes. This glitch can
>>easily be observed with a simple CMOS invertor with a fast (100 psec)
>>ramp as the input of the invertor, I think this glitch is because of the
>>stored charge in the depletion region of upper and lower devices.
>>
>> I will send a simple SPICE file that I have been using to simulate this
>>effect. The SPICE version which I am using runs into convergence problems
>>if I remove Cd1 capacitor. This capacitor presents the die capacitor in
>>IBIS models. After the simulation the voltage at node 2 should be probed.
>>
>>Best Regards,
>>Peivand Tehrani.
>>
>>
>>**************************SPICE file************************
>>
>>
>>
>>Driver Device Transitions For Gate Transition
>>*************************************************************
>>VDD 3 0 5
>>*************************************************************
>>M1 2 1 0 0 QN L=1.5E-6 W=136.4E-6
>>M2 2 1 3 3 QP L=1.5E-6 W=341E-6
>>*************************************************************
>>.MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 )
>>.MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200)
>>*************************************************************
>>VIN1 1 0 PULSE(5 0 0 .01n 0 100E-9 1E-3)
>>*************************************************************
>>Cd1 2 0 4p
>>R11 2 0 50
>>*************************************************************
>>.tran .001n 1n
>>.END
>>

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Subject: Re: Stored Charge by Peivand Tehrani
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