Re[3]: Stored Charge by Peivand Tehrani

Arpad, Bob and Sung,
 
  This is a good observation, my point was that the "glitch" exists
and may propagate along a signal line. As arpad has shown, depending
on the value of the parasitic capacitors, the loading and the gate
risetime, magnitude of this glitch will change.
  This effect is a device property and although it is small, in order
to get accurate device simulation, it has to be modeled.
  The[xxxxing waveform]s can only provide the magnitude of this glitch
under a certain loading condition. Note that in the invertor case, the
glitch causes the buffer low to high transition trajectory (id(m1)-id(m2)
vs. v(2)) to jump out of the device [pullup] and [pulldown] I/V
characteristics. This is dynamic effect and without knowing the exact
gate transition waveform (which is the case in IBIS), the values of the
parasitic capacitors can not be extracted from the provided information.
  The glitch has a current associated with it which is provided by either
one of upper and lower devices. Without knowing the value of the parasitic
caps. it is hard to divide this current between the devices.
  Do you have any suggestions as to how I can approach this problem using
the provided IBIS information?
  
Best regards
peivand
Received on Wed Jul 24 08:49:18 1996