Re: questions on ibis

Walter:

You raised some good questions. I have some comments in
your questions which may help.

Best Regards
Bob Ross
Interconnectix

>Date: Thu, 02 Oct 1997 09:02:15 +0200
>From: Schneider Walter <schwa1@fh-landshut.de>
>Organization: Fachhochschule Landshut
>To: ibis@vhdl.org
>Subject: questions on ibis

>
>Hello!
>
>After creating some ibis-modells and simulating with them, I have
>now some questions:
>
>1) Does anyone know, what voltage step (u/i-tables) is normally used?
> I had the problem that by taking a step of 0.1V some oscillations
> occured when simulating a transmission line. By increasing the
> step up to 0.5V these oscillations disappeared.
> What can be the reason for this?

I would have to see the test circuit, results, and full model to figure
out what is expected and how bad the results are. This could also
be dependent on what simulator is used and its internal algorithms.
There could be a numerical processing issue related to internal
time steps that may induce or kill the oscillation. In general,
I would expect that you would get better results with more
data points if they are continous-like in nature.

>
>2) The ibis-specification defines what voltages, temperatures and
> process parameters have to be used for simulating worst/best case
> conditions only for TTL- and CMOS-technologies?
> What should be used for ABT (advanced BICMOS technology) or
> BCT (BICMOS technology)?

Still use low voltage, slow-weak process for the min column, and
the opposite for the max column. The real issue what temperature to
use. My first approach was to base the temperature on the output
stage technology. However, when I tried this, it did not give me
the fastest or slowest responses. So I now try both temperature
extremes and take the temperature which gives me the slowest rise
and fall times for the min column, and fastest rise and fall times
for the max column. In one ABT case this worked out to be the
highest temperature for the min column, and lowest temperature for
the max column.

>
>3) By creating the u/i-tables from actual silicon measurements
> the voltage sweep (-VCC ... +2VCC) must be reduced.
> To cover the recommended region the specification says to make
> an extrapolation.
> Has anyone ever made such an extrapolation and compared the
> simulation results with an ibis-modell without the extrapolation
> (i.e. reduced u/i-tables) ?

Many behavioral simulators automatically do extrapolation of the
VI table endpoints. So the results should be the same even if
the extrapolated data is not provided. However, when tranforming
the IBIS data into a Spice syntax using table based controlled
voltage or controlled current sources, there will be a difference.
Most Spice simulators will truncate the tables to the endpoint
current values if the voltages are outside of the table range.
So if a reflected signal actually causes a voltage outside
of the table value, the result should be different.

IBIS contains the range requirements so that all types of simulators
will process the same set of data.

>
>
>I hope I hear from you soon!
>
>Thank you very much!
>
>
>
>email: schwa1@fh-landshut.de
>
>mail: Walter Schneider
> Muehlweg 25
> 94513 Schoenberg
> Germany
> phone: 08554/3916
>

 
Received on Thu Oct 2 13:34:54 1997