Hi Chen,
Here is my take. There are three major classifications for
models to get into a board level signal integrity evaluation.
First, IBIS models for buffer modelling.
Second, analog and jelly bean parts such as
resistors, capacitors, switches, etc. are
typically modelled as very small spice like models.
(Each vendor has their own little language parsers)
Third, connectors. Since IBIS support is supposedly on
the way, the signal integrity engine providers have
to currently offer their own language modelling support.
It is usually a primary RLC matrix with mutual inductance and
mutual capacitance specifications for the pins.
Good question!
Thanks,
Fawn _/ Fawn Engelmann
_/ _/ email: fawn@emc.com
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_/ _/_/ _/_/ _/ _/ Fax: (508) 497-8741
_/_/_/_/ _/ _/ _/ _/ _/_/_/
_/ _/ _/ _/ EMC Corporation
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Hopkinton, MA 01748-9103
_/"THE Storage Architects"_/ http://www.emc.com
Received on Fri Oct 17 07:33:02 1997
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