RE: Correlating IBIS models with actual Silicon measurements

Dear Amlan,

These are excellent questions, and I commend TI for pursuing lab
verification of IBIS datasheets (models). This effort - and it is an
effort - results in increased user confidence in your products. I wish
I could tell you there is one place to look for this information. These
two chapters in the IBIS Cookbook are presently under construction, as
you probably already know. (If you're not familiar with the Cookbook,
you can find it at the IBIS web site, www.eia.org/eig/ibis/ibis.htm.)
In addition, I am serving on an IBIS subcommittee which is writing a
specification for datasheet accuracy; we plan to have ready it for first
review in September 1998. It is our intention to make the IBIS Accuracy
Specification a document of understanding between the component user and
vendor so that both parties know exactly what constitutes an accurate
IBIS datasheet.

In the meantime, perhaps I can offer some assistance. (My company buys
a lot of parts from yours, so we have more than an altruistic interest!)

You won't be able to independently measure the IBIS keyword C_comp on a
packaged part. In general, there are four components to pin
capacitance, working in from the pin: the package, the die bond pad,
the ESD protection devices, and the FETs associated with the I/O buffer
circuit. When you measure pin capacitance on the packaged part, you get
all of these lumped together. (Sometimes they're not really lumped,
like when you have on-chip series termination.) This means that you can
only verify the sum of C_comp and C_pkg (or C_pin). Of course, if you
have a package with no die in it, you can isolate C_pkg.

We have been struggling quite a bit with capacitance measurements on a
test board that our subcommittee designed to demonstrate lab
verification of IBIS datasheets. I am trying to make the measurements
using an HP4275A LCR meter, which employs an autobalancing bridge.
There was some excellent discussion on the SI reflector in the last two
weeks around how to measure pin capacitance. I could forward you some
of these notes, if you're interested.

IBIS defines the ramp parameters WITHOUT the package, which is feasible
in SPICE but not in the lab. I believe the intention is to capture the
intrinsic rise and fall times of the driver, which may then be used with
any package circuit by simply changing C_pkg, etc. However, this
presents some difficulty when correlating hardware against the
datasheet. If you have the SPICE model available to you, I would
recommend extracting dV/dt_r and dV/dt_f from SPICE waveforms, as
described in IBIS, with and without the package model to see how big an
effect to expect. You can then take your lab measurements for these
sub-parameters and apply a correction factor. Finally, when you feel
reasonably confident in your datasheet parameters, use a behavioral
simulator to generate waveforms for the IDENTICAL NETWORK that you used
to measure the waveforms in the lab. Include probe capacitance and
bandwidth effects in your behavioral simulation. Measure Zo and Tpd of
your transmission lines and put these values in your behavioral
simulations.

I'm not sure why you're interested in the input of the driver. IBIS
doesn't directly address I/O buffer delays.

My colleague and I presented a paper on behavioral model accuracy at
DesignCon98 in Santa Clara, CA. If you'd like a copy, just send me your
address. Also, keep an eye on the IBIS reflector in the next month or
two. Our subcommittee will be posting the design of the test board I
mentioned.

Sincerely,
Greg Edlund
----------
Greg Edlund, Principal Engineer
Server Product Development
Digital Equipment Corp.
129 Parker St. PKO3-1/20C
Maynard, MA 01754
(978) 493-4157 voice
(978) 493-0941 FAX
greg.edlund@digital.com

        ----------
        From: Amlan Chakrabarti[SMTP:tatai@india.ti.com]
        Sent: Monday, April 27, 1998 5:52 AM
        To: ibis@vhdl.org
        Cc: tatai@india.ti.com
        Subject: Correlating IBIS models with actual Silicon
measurements

        Hi,
         We at Texas Instruments (India) are trying to develop IBIS
models for one of our
        products .We have a few questions regarding the correlation of
IBIS models
        (generated through simulation) with actual Silicon measurements
-
            
            1.How can we measure the "input die capacitance"in the lab ?
            
            2.How can we measure the output rise/fall times when the
chip is available
              in a plastic package ?Unless we open the package only the
enable pin of
              an output buffer is available to us(along with the output
pin)-but we can't
              access the input of the buffer.
                          Can you send us any information regarding the
correlation of IBIS
              models with Silicon ?Any URL's having such information
will be very helpful
              for us.
                                                               Thanks
and best regards,
                                                                Amlan
Chakrabarti.
                                                                Texas
Instruments (India) Ltd.
                                                                E-Mail :
tatai@india.ti.com
              
Received on Mon Apr 27 06:53:24 1998