Re: IBIS BIRD59 MODEL SPEC DIAGRAMS

Al:

Thank you for your comments. I considered them while preparing
BIRD59.1 along with other input discussed at the IBIS Open Forum
meeting today (August 6, 1999).

BIRD59.1 should follow shortly.

The main addition is to add some minor detail concerning switching
regions on the hystersis diagram.

I have inserted some comments in your text below since I believe
that your interpretation of Vinh and Vinl is not the one that has
been used in industry since IBIS Version 1.1 issued in 1993.

Best Regards,
Bob Ross
Mentor Graphics

Al Davis wrote:
>
> I still find the descriptions to be confusing.
>
> The [Model Spec] group seems to have the purpose of describing how the
> analog representation of a waveform is interpreted as digital,
> evaluating its logic state and quality.
>
> My original interpretation of the old (pre model spec) Vinl and Vinh
> is as follows:
>
> The logic value switches from a "logic low" to a "logic high" when a
> rising signal crosses through Vinh. It switches from "logic high" to
> "logic low" when a falling signal crosses through Vinl.
>
> In a static sense, a voltage below Vinl indicates a "logic low" state,
> above Vinh indicates a "logic high" state, and between is unknown, in
> transition.
>

This is too restrictive. Vinl and Vinh values are "specification"
values showing the range in which the rising waveform edge can switch.
The same range is used for the falling edge.

For example, a common specification is Vinl = 0.8 and Vinh = 2.0. The
actual device switching region may be around 1.3 to 1.5 Volts. However,
due to temperature, process variations, voltage variations, receiver
risetime, etc. (and conservative specification), the actual switching
may float up and down within the 0.8 to 2.0 Voltage band.

So, for a rising edge, the input may switch as early as 0.8 Volts and
as late as 2.0 Volts. Similarly for the falling edge. This has been
used for years for analyzing corner cases for slowest and fastest cases.

> On further reading, I believe this may not be the proper
> interpretation.
>
> Other parts of the spec lead me to believe that the intended
> interpretation is:
>
> The logic value switches from a "logic low" to a "logic high" when a
> rising signal crosses through Vinl. It switches from "logic high" to
> "logic low" when a falling signal crosses through Vinh.
>
> Note interchange of Vinl and Vinh, compared to above. This seems
> illogical to me, but clarifies (sort of) some of the other
> parameters, and fits with the note on how to "mimic a hysteresis
> effect" using only Vinl and Vinh.
>

Again, this interpretation is too restrictive. The Vinl and Vinh values
bound the allowable swithing region of BOTH the rising and falling edges.
The actual switching point will normally occur somewhere in between these
specification limits.

> Another interpretation could be:
>
> The logic value switches from a logic low to "rising" when a
> rising signal crosses through Vinl, then finally switches to logic
> high on crossing Vinh. It switches from logic high to "falling" when
> a falling signal crosses through Vinh, then switched to "logic low" on
> crossing Vinl.
>
> This adds the notion of an in-transition state, when the logic state
> is neither high nor low, and possibly creates a use for the new
> hysteresis parameters.
>
> The composite (with the new hysteresis parameters) could be
> interpreted as ......
>
> The logic value switches from a "logic low" to "rising" when a rising
> signal crosses through Vinl
>

You are on the right track related to a proposed extension to IBIS for
Version 4.0. The details of the actual signal transition at the input
are now becoming important factors in characterizing Tco (clock to output
delays) and other characteristics. However, the Vinl and Vinh values
themselves do not define how an input starts and ends the transistion.
As stated before, it defines the endpoints in which a much narrower
(in most cases) switching band can be positioned.

> Now, add "[Model Spec]" ....
>
> It, too, has a Vinh and Vinl, this time with a min and max. I wonder
> why it is necessary to have it twice. Why not just add optional min
> and max fields to the original? or move the existing parameters to be
> under ModelSpec, for consistency? The same applies to Vmeas.
>

No change will be made for the above reasons that revise your interpretation.
The min and max column already within the [Model Spec] keyword already
give a way of producing a much narrower band (if known) based on Voltage,
Temperature, and Process variation extremes for the defined corners.

> It is still not clear what the hysteresis parameters do. It appears
> to me that hysteresis can be adequately described without the new
> parameters. What actually happens at Vinh+, Vinh- ? How does this +
> and - differ from the min and max columns? This is still not clear.
>

In response to this and other comments, I will add some detail to the
diagram to highlight the switching regions. I also refer to this as
a Schmitt trigger input. Its operation is commonly known in industry
and often referenced in data sheets for ASIC buffers.

> --------------------
>
> On the "overshoot" parameters ......
>
> Add:
>
> The purpose of the "overshoot" and "pulse" groups of parameters is to
> determine the quality of an incoming signal.
>
> A signal is considered to be "bad quality" if:
>
> 1. V ever exceeds D_overshoot_high
> 2. V ever drops below D_overshoot_low
> 3. V exceeds S_overshoot_high longer than D_overshoot_time
> 4. V drops below S_overshoot_low longer than D_overshoot_time
>

While more can be stated in the Specification regarding
overshoot and pulse immunity subparameters, their intent is not
exactly as you have stated. So this text is not entered.

They are not used for "quality", but rather for additional
specification detail. Overshoots are given regarding
physical devices limits for voltage levels which would
destroy (of effectively destroy the device by changing
its characteristics). These are typically above and
below the voltage rails. The dynamic overshoot gives
an allowable extension window which for a short period of time
allows greater overshoot voltages. This is not perfect.

The simulator then can choose to test against RULES
regarding these limits. This is often a pass or fail
test based on these "specification" limits (or on
alternative levels against which to test that the
user might insert into the IBIS model). I believe
this is becomes a more serious issue when the physical
device does not have clamping to a particular voltage
rail at that pin.

> --------------
>
> the "pulse" parameters ....
>
> The wording is still unclear. The words and picture conflict with
> each other, probably because of the confused interpretation of Vinh
> and Vinl.

While not perfect I hope the diagram gives some help when considering
Vinh and Vinl as a specification band limit and considering
that pulse immunity parameters give a method to exceed that limit
for a short period of time.
Received on Fri Aug 6 16:01:41 1999