Re: BIRD #61

D. C. Sessions wrote:
>
> Fred Balistreri wrote:
>
> > Hello Arpad, I'm curious about how the delay numbers wrt slope are
> > measured or derived from. I realize you may not be the right person to
> > ask. My question is very fundamental. Are we measuring these parameters
> > and if so how. Or are we relying on SPICE simulations? In other words
> > we are trying to determine the conditions upon which an input stage
> > accepts a "high" or "low" state. On a VVLSI device how does one measure
> > this? Do semiconductor vendors really put test points inside the
> > input stage to probe? If not what techniques are going to be used to
> > assure of the numbers? I'm having a hard time understanding how the
> > numbers are derived and if they can be trusted.
>
> I'll answer this. Basically, we SPICE the input variation with
> stimulus waveforms. The actual setup and hold times are also
> derived from simulation but are regressed by our test group
> during characterization. One of the reasons we chose to propose
> the table-based method is that it's possible for physical model
> services to measure delay variation by testing setup and hold
> variations against the input waveform sets.
>
> --
> D. C. Sessions
> dc.sessions@vlsi.com
Have you found a direct equation or coorelation between setup and
hold time variation vs delay variation due to slope change? Is it
exactly one to one? And sort of consistant for all parts?, technologies?
If so would you be willing to share the information with service
model providers?

On a VVLSI device where the signal propagates through perhaps several
stages is not the variation of setup and hold also do to those stages
as well as the input buffer? In IBIS are we trying to do through gate
delay or define acceptable input voltage thresholds?

Best Regards,

-- 
Fred Balistreri
fred@apsimtech.com
http://www.apsimtech.com