RE:

Janne,

You are correct that the power supply and ground package
parasitics will also effect the behavior of the buffers.

However, you are not correct in saying that IBIS assumes
ideal supply rails around the buffers. You can define
package parasitics for Vcc and GND pins as well as for
signals in the IBIS model. IBIS is only lacking in the
description of die interconnects. In other words, it
doesn't give you enough detail on how the power pins (or
die pads) are connected with the buffers on the die.

It is another question whether simulator tools connect
the buffer model through the package parasitics or just
to an ideal source.

Arpad Muranyi
Intel Corporation
===========================================================

-----Original Message-----
From: janne.ikavalko@nokia.com [mailto:janne.ikavalko@nokia.com]
Sent: Monday, March 20, 2000 1:48 AM
To: ibis@vhdl.org
Subject:

Hi Everybody!

It came to my mind, that how does simulation with IBIS models take into
account
parasitics which comes from power supply and ground pins and bonding wires?
As I understand only signal line's pin and bonding parasitics are included
into the simulation.
However, I think that in real life parasitics from power supply and ground
bonding wires has some effect also.

My current opinion is that effect from power supply and ground bonding wires
are not taken into account. Connection to power supply and ground are
considered ideal.
Am I right?

I tried to find information about this from IBIS specifications, but I
couldn't find any.

What is Your opinion, how (much) does this effect to the correctness of the
simulation result?
 

Best Regards,
                    Janne Ikavalko

-- Janne Ikavalko
-- NMP Tampere, Finland
-- GSM +358 50 3655120
-- Janne.Ikavalko@nokia.com
Received on Mon Mar 20 08:35:19 2000