RE: Question regarding c_comp

All,

IBIS does contain two references to pad capacitance.
First through c_comp and second through the V:T tabular
data.

Note that some behavioral simulators want the pad
capacitance removed for generation of V:T curves.
Therefore, use of valid IBIS models in these tools
will double count the parasitics resulting in slewed
edges. The slower edge rates result in better signal
quality and predict inaccurate flight times.

Moral of the story: know the limitations of your tool
before simulating.

Frank Kern
Performance Processor Division
Intel Corporation

-----Original Message-----
From: gedlund@us.ibm.com [mailto:gedlund@us.ibm.com]
Sent: Thursday, May 25, 2000 3:12 PM
To: Dave MacAdam
Cc: ibis@vhdl.org
Subject: Re: Question regarding c_comp

Dave,

C_comp represents all on-chip capacitance and needs to be set to the value
that correctly represents your FETs, ESD devices, and bond pad. The IV
curve part of the model data does not contain any capacitance information,
so you won't be double counting. If you are using s2ibis2, there is a
parameter in the control file that sets C_comp. You should use min, typ,
and max values. I think the best way to get the correct value is to ask
your SPICE program to print the appropriate device capacitance values and
tally them up. I always check C_comp by running behavioral and HSPICE
simulations with 1 ns open-ended transmission line on the output of the
driver. Let the wave slosh back and forth a few times and you'll see if
you got the capacitance right. (Thanks to Ross Pryor for this technique.)

There is a better list for user-related questions: ibis-users@vhdl.org.
The list you posted to tends more toward development-related topics. If
you want more information about making IBIS datasheets, check out the
cookbook under "free tools" or the accuracy handbook under "accuracy" on
the IBIS web site.

Good luck.

Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com

Dave MacAdam <dsm@adc.idt.com> on 05/25/2000 10:02:37 AM

To: ibis@eda.org
cc:
Subject: Question regarding c_comp

I hope this is the correct address to post this type of question, if not

I apologize.

I'm confused about the usage of c_comp in my model. The pad that I'm
attempting to create a model for is being simulated using an extracted
netlist, which will include all pad capacitance (structure, esd etc.).
As I understand it, c_comp is the input cap of the input pin, and
therefore is contained in my netlist used to generate the I-V curves.

With this, should I put c_comp to zero else be 'double counting' this
capacitance when the user simulates using my model?

Thanks

Dave MacAdam

----------
Design Engineer
Integrated Device Technology, Inc.
Atlanta Design Center
Received on Thu May 25 15:35:58 2000