RE: BIRD 68.1

Hi Adam,

Well, you are pretty close. The Bird clarifies IBIS in hope that--if
everytning is done correctly--you will not see duty cycle distortion in
simulation. Hence, as you say, the V-T tables should begin at the same time
with respect to some edge stimulus inside the device you are modeling. Any
difference in delay between rising a falling edges should be represented by
where the actual edge occurs in the respective tables. You should not need
to manually add any additional delay; the data from your transistor level
simulator should do that for you if it is modeling the differences in
internal delays already.

If you are taking bench data on real silicon, then you will need to build
the tables to show the differences in delays. Your digital scope might do
that for you if you are triggering from a common clock, for example.

But in addition to all of the above, the simulator you are using must also
handle the waveforms correctly, in order to avoid the duty cycle distortion.
Some may, others may not. It is always a good idea to run some correlation
simulations to compare with the bench test data or transistor level
simulator to make sure it is all working the way it should be.

Best regards,
David Lorang

-----Original Message-----
From: Adam.Tambone@fairchildsemi.com
[mailto:Adam.Tambone@fairchildsemi.com]
Sent: Tuesday, June 12, 2001 10:51 AM
To: ibis@eda.org
Subject: BIRD 68.1

Hello All,

I have question regarding BIRD 68.1. Does the BIRD state that if the
recommendations within it are followed ( i.e. if the v-t tables for rising
and falling begin at the same time as the rising and falling edges of the
input stimulus, and additional delay is introduced to account for delay not
within the buffers ) then undistorted duty cycles will be represented in
simulation?

Thanks,
Adam Tambone

 
Received on Tue Jun 12 16:40:41 2001