BIRD 68.1

Bob and David,

Thank you both for your responses. They have led me to more questions,
please excuse their simplicity.

Bob, I am not clear about your statement, "they have to be offset by the
same amount of time".

Can you provide more description?

David, The netlists we use in S2I translation include only the buffers (
we are currently considering using netlists that include full data paths
instead ) and so my question is, should additional delay be added to the
rising and falling waveforms to account for the delay through circuitry not
included in these netlists?

Another question.

Since the rising and falling edges represented in the rising and falling
waveforms were gained with an input stimulus with a specific trise and
tfall, is it necessary for the simulations to be run with the same trise
and tfall on the input stimulus? In other words, if simulations are run
with an input stimulus that has different trise and tfall then that of the
input stimulus used to produce the rising and falling waveforms will not
the edge rates in simulation be invalid?

Thank You Again,
Adam Tambone

Adam:

The rising and falling V-T tables do not have to
start at the same time as the input stimulus, but
they have to be offset by the same amount of time.

Then the buffers should simulate in an undistorted
manner - provided that the pulse width is wide
enough to capture the whole rising and falling
waveforms. The pulse width can be reduced if
a leading edge delay time removal algorithm is
used to remove equal delays in both rising and
falling waveform sets.

Bob Ross
Mentor Graphics

Hi Adam,

Well, you are pretty close. The Bird clarifies IBIS in hope that--if
everytning is done correctly--you will not see duty cycle distortion in
simulation. Hence, as you say, the V-T tables should begin at the same
time
with respect to some edge stimulus inside the device you are modeling. Any
difference in delay between rising a falling edges should be represented by
where the actual edge occurs in the respective tables. You should not need
to manually add any additional delay; the data from your transistor level
simulator should do that for you if it is modeling the differences in
internal delays already.

If you are taking bench data on real silicon, then you will need to build
the tables to show the differences in delays. Your digital scope might do
that for you if you are triggering from a common clock, for example.

But in addition to all of the above, the simulator you are using must also
handle the waveforms correctly, in order to avoid the duty cycle
distortion.
Some may, others may not. It is always a good idea to run some correlation
simulations to compare with the bench test data or transistor level
simulator to make sure it is all working the way it should be.

Best regards,
David Lorang

> Adam.Tambone@fairchildsemi.com wrote:
>
> Hello All,
>
> I have question regarding BIRD 68.1. Does the BIRD state that if the
> recommendations within it are followed ( i.e. if the v-t tables for
rising
> and falling begin at the same time as the rising and falling edges of
the
> input stimulus, and additional delay is introduced to account for delay
not
> within the buffers ) then undistorted duty cycles will be represented in
> simulation?
>
> Thanks,
> Adam Tambone

 
Received on Wed Jun 13 08:14:13 2001