Subject: [IBIS] Terminated buffer
From: Shee Kian Wong (SKWONG@altera.com)
Date: Thu Oct 10 2002 - 00:10:42 PDT
Hi IBIS users,
I'm currently modeling a terminated buffer (a buffer with built-in
termination resistor) but it seemed that the traditional method did not
work.
Does anyone has experience in modelling terminated driver and receiver (e.g.
gtl, sstl-3)?
Best Regards,
Shee Kian Wong
Applications Engineer
_____________________
Altera Corporation (M) S/B
Bayan Lepas Technoplex,
Medan Bayan lepas,
11900 Penang, Malaysia.
Tel: +604 636-6185
Fax: +604 642-8525
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