Subject: RE: [IBIS] Terminated buffer
From: Tom Dagostino (tom@teraspeed.com)
Date: Thu Oct 10 2002 - 08:40:39 PDT
Terminated bufferI'll bet the problem you are having is double counting the
pull-up resistor. If you try to model the buffer as a traditional output
the IV curve you get for the pull up will be OK. The IV curve for the pull
down will also have the pullup resistor included since it does not get
turned off like the pull up device in a standard CMOS buffer. To model such
a buffer you have to put the pullup resistor's model in the power clamp and
subtract its effect from the pull down characteristics for the pull down
table.
Tom Dagostino
Device Modeling Division
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 430-1065
-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org]On
Behalf Of Shee Kian Wong
Sent: Thursday, October 10, 2002 12:11 AM
To: 'ibis@eda.org'
Subject: [IBIS] Terminated buffer
Hi IBIS users,
I'm currently modeling a terminated buffer (a buffer with built-in
termination resistor) but it seemed that the traditional method did not
work.
Does anyone has experience in modelling terminated driver and receiver
(e.g. gtl, sstl-3)?
Best Regards,
Shee Kian Wong
Applications Engineer
_____________________
Altera Corporation (M) S/B
Bayan Lepas Technoplex,
Medan Bayan lepas,
11900 Penang, Malaysia.
Tel: +604 636-6185
Fax: +604 642-8525
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