Subject: [IBIS] IBIS criticalities for SiP simulations
From: Antonio Girardi - 20021115 (antonio.girardi@st.com)
Date: Wed May 28 2003 - 00:21:23 PDT
Hello everybody,
I need to submit you some criticalities releated to IBIS simulations.
I am doing a comparing between IBIS and SPICE level simulations and
I have identified some limits of actual standard IBIS.
The criticalities are the following
1) IBIS does not include informations about the total capacitance
releated
to die power/ground nets. This values are very important during SSN
simulation.
Comparing IBIS netlist with SPICE one, when a RLC package parassitic
parameters are inserted on VDD/GND nets, the results are very different
because of absence of die power/gnd capacitance in IBIS model.
2) IBIS does not support electrical paths between VDD and GND of buffer
control logic. In other terms, when an oscillation is present on VDD
node his
time loss depends not only of final buffer characteristics but also of
any active electrical
path of control logic between VDD and GND. These paths help the loss of
oscillation.
3) Parasitic diodes between VDD and GND are not supported.
These diodes could have a frequency spectrum which can favourite
the loss of Vdd oscillations.
I hope you could help me because the SSN simulations with IBIS model are
very
important in order to design system-in-package devices.
Thanks in advance for your support.
Best regards,
Antonio Girardi
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