Subject: RE: [IBIS] IBIS criticalities for SiP simulations
From: Peters, Stephen (stephen.peters@intel.com)
Date: Wed May 28 2003 - 13:14:25 PDT
Greetings Antonio:
You are correct that IBIS models do not generally include information on
the total die capacitance or the electrical paths between VDD and GND. IBIS
is generally focused on the switching characteristics of the I/O buffer
itself. However, there is a workaround. You can use the [Series Pin
Mapping] keyword to create a connection between a VDD and GND pin, then use
one or more of the [Series] keywords to define and place a model between the
two pins. For example, you can use [C series] to define a VDD to GND
capacitance, or [Series Current] to define a non-linear resistance between
VDD and GND.
Note that for this technique to work your simulation tool must support the
[Series] keywords. Your tool must also support the idea of non-fixed power
supply rails.
Hope this helps.
Regards,
Stephen Peters
Intel Corp.
-----Original Message-----
From: Antonio Girardi - 20021115 [mailto:antonio.girardi@st.com]
Sent: Wednesday, May 28, 2003 12:21 AM
To: ibis@eda.org
Cc: Antonio GIRARDI
Subject: [IBIS] IBIS criticalities for SiP simulations
Hello everybody,
I need to submit you some criticalities releated to IBIS simulations.
I am doing a comparing between IBIS and SPICE level simulations and I have
identified some limits of actual standard IBIS.
The criticalities are the following
1) IBIS does not include informations about the total capacitance releated
to die power/ground nets. This values are very important during SSN
simulation. Comparing IBIS netlist with SPICE one, when a RLC package
parassitic parameters are inserted on VDD/GND nets, the results are very
different because of absence of die power/gnd capacitance in IBIS model.
2) IBIS does not support electrical paths between VDD and GND of buffer
control logic. In other terms, when an oscillation is present on VDD node
his time loss depends not only of final buffer characteristics but also of
any active electrical path of control logic between VDD and GND. These paths
help the loss of oscillation.
3) Parasitic diodes between VDD and GND are not supported. These diodes
could have a frequency spectrum which can favourite the loss of Vdd
oscillations.
I hope you could help me because the SSN simulations with IBIS model are
very
important in order to design system-in-package devices.
Thanks in advance for your support.
Best regards,
Antonio Girardi
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