Re: [IBIS] Re: R-Load

Andy,

Thanks for clarifying this.

The other concern i had was
a. How does the  V/T data(Ramp) and I/V data
get used up at the boardlevel when simulted by a tool.

As far as my knowledge goes ramp rate is imp but not V/T data
for o/p and bidi buffers. I/V data generally depicts the drive strength
of a buffer, how does this correlate into tranisient behaviour by
board level tool when data(swicthing from 1 to 0 and 0 to 1 at some freq)
is applied at dummy i/p pin.

Do we have some documnt (board design) to understand how the IBIS data
is interpreted by the signal integrity tool.

Thanks again for your reply.

Regards
vinayak

Andrew Ingraham wrote:

>>I had this query as to why we need to model the buffers with R-load
>>as in most of the cases it is c-load w/without TL line is
>>driven by the buffer).
>>
>>does it reflect on the TL impedence that it drives? (50ohm environment)
>>    
>>
>
>I think you hit the nail right on the head.
>
>If the buffer drives a transmission line that is 3 ns long, the device sees
>an effective load of Zo (typically in the vicinity of 50-80 ohms) for the
>first 6 ns after it switches.
>
>Regards,
>Andy
>
>
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