To Attendees: We are looking foward to seeing you next week. Please come early to sign in since many people are registered. Please bring a business card to serve as your meeting badge. Bob ------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: 8:15 - 17:30, Friday October 27, 2006 Location: Radisson Hotel Shanghai New World 88 Nanjing Road (W) Shanghai 200003 CHINA Tel: + 86-21-63599999 Fax: + 86-21-63589705 E-mail newworld@radisson-nw.com Room: Check Hotel Meeting Listing Sponsors: Huawei Technologies (Primary) Ansoft, Cadence Design Systems, Intel Corporation Mentor Graphics Corporation, Signal Integrity Software (SiSoft), Sigrity, and Synopsys ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 8:15 REFRESHMENTS & SIGN IN - Vendor Tables Open 9:00 Welcome and Keynote Comments - Jiang, XiangZhong (Huawei Technologies, China) - Mirmak, Michael (Chair., EIA IBIS Open Forum, Intel Corporation, USA) - Xu, ShaoMin (Chairman and Managing Director, Shanghai Government Information Technology Committee, China) 9:30 The Direction of IBIS as a Standard Mirmak, Michael (Intel Corporation, USA) 9:45 IBIS Model Validation Report Zheng, Qi (Fiberhome Telecommunications Technology, China) 10:15 BREAK (Refreshments) 10:30 IBIS Model Engineering for SI Analysis Kusunoki, Kazuhiko (Cybernet Systems, Japan) 11:00 Case Study: Spice Macromodeling for PCI Express Using IBIS 4.2 Wang, Lance (Cadence Design Systems, USA) 11:30 System-Level Timing Closure Using IBIS Models Katz, Barry (Signal Integrity Software (SiSoft), USA) 12:00 FREE BUFFET LUNCH (Hosted by Sponsors) - Vendor Tables - Press Luncheon for IBIS Officers and Sponsors 13:30 Statistical Eye Simulation Requirements Huang, ChunXing (Huawei Technologies, China) 14:00 Methodologies for Multi-Gigabit Interconnect Design Byers, Andy, and Williams, Lawrence (Ansoft Corporation, USA) 14:30 System-Level SSO Simulation Techniques with Various IBIS Package Models Chitwood, Sam*, Lin, Jack, W.C.**, and Chen, Raymond Y.* (Sigrity, *USA and **China) 15:00 Using S-parameters for Behavioral Interconnect Modeling Zhu, ShunLin (ZTE Corporation, China) 15:30 BREAK (Refreshments) 15:45 JEITA EDA - WG Activity and Study of Interconnect Model Part-3 Watanabe, Takeshi*, Ikeda, Hiroaki**, and JEITA (*NEC Electronics, **Japan Aviation Electronics, Japan) 16:15 IBIS 4.2 and VHDL-AMS for Serdes and DDR2 Analysis Dodd, Ian and Pratt, Gary (Mentor Graphics Corporation, USA) 16:45 IBIS Modeling of DDR2 in Conjunction with Linear Channel Analysis Dodd, Ian (Mentor Graphics Corporation, USA) 17:05 ODT, Pre-Emphasis, and Speed Ross, Bob (Teraspeed Consulting Group, USA) 17:20 Concluding Items 17:30 END OF IBIS SUMMIT MEETING - Final Vendor Tables and Teardown ------------------------------------------------------------------ -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Labs 121 North River Drive 13610 SW Harness Lane Narragansett, RI 02882 Beaverton, OR 97008 401-284-1827 503-430-1065 http://www.teraspeed.com 503-246-8048 Direct bob@teraspeed.com Teraspeed is a registered service mark of Teraspeed Consulting Group LLC -------------------------------------------------------------------- |For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org |with the appropriate command message(s) in the body: | | help | subscribe ibis <optional e-mail address, if different> | subscribe ibis-users <optional e-mail address, if different> | unsubscribe ibis <optional e-mail address, if different> | unsubscribe ibis-users <optional e-mail address, if different> | |or e-mail a request to ibis-request@eda-stds.org. | |IBIS reflector archives exist under: | | http://www.eda-stds.org/pub/ibis/email_archive/ Recent | http://www.eda-stds.org/pub/ibis/users_archive/ Recent | http://www.eda-stds.org/pub/ibis/email/ E-mail since 1993Received on Thu Oct 19 17:37:43 2006
This archive was generated by hypermail 2.1.8 : Thu Oct 19 2006 - 17:38:35 PDT