RE: [IBIS] About Fork in The Package Model

Of course I remember them... You are correct, the "Fork"
syntax can be used for that, but the problem is that
strictly speaking the package syntax doesn't allow you
to name the instance of devices (U1, U2, U3, etc...) on
the chip's end of the package.

The EBD syntax does allow you to do that, but I am not
sure whether EDA tools allow people to use that as if it
was the package... That was really designed for describing
the memory DIMM modules. It might be worth a try, though,
I just don't have any experience with doing it...

Arpad
=============================================================

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Todd
Westerhoff
Sent: Thursday, May 26, 2011 7:22 AM
To: 'ibis@server.eda-stds.org'
Subject: RE: [IBIS] About Fork in The Package Model

Arpad (& all),

Remember plating bars? **

Plating bars were standard features of some packages circa 1998 (if I
remember correctly). Getting gold to deposit on traces is an
electrochemical process, which required voltage to be applied to the
traces while in the solution. Every signal to be plated connected to a
common "bar" that had voltage applied to it. After plating, the "bar"
was
cut away, leaving trace stubs hanging around the outside of the package.

We used to use the IBIS fork syntax to model those hanging stubs, and it
worked just fine. As for any connection strategies other than 1:1 - I
believe you're right, it's a no-go.

Todd.

** This is the point in the conversation where us old-timers can wax
sentimental about how life was in the old days, when we had to walk 5
miles to and from elementary school (uphill both ways), in the bitter
cold, knee-deep in driving snow, all the while having to be on the
look-out for rabid, wild animals. For anyone under 30 who can't
visualize
such a thing, There's an App for That.

Have a great day!

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of
Muranyi,
Arpad
Sent: Wednesday, May 25, 2011 6:26 PM
To: ibis@server.eda-stds.org
Subject: RE: [IBIS] About Fork in The Package Model

Johann,

Unfortunately the IBIS package model cannot do any forks or joins. The
assumption in IBIS currently is that there is a 1 to 1 mapping between
pins and pads.

This is not going to help you in the short run, but it is kind of funny
that we just talked about this in the IBIS Interconnect Task Group
meeting
today...

We are aware of the problem and we are trying to come up with a
solution,
hopefully for the next major IBIS spec.

Arpad
=====================================================

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of
Nittmann, Johann
Sent: Wednesday, May 25, 2011 3:14 PM
To: ibis@server.eda-stds.org
Subject: RE: [IBIS] About Fork in The Package Model

Hi,

A particular signal in one of our packages is using a fan out (fork) to
4 locations on the die. Hence I am considering of defining a [Package
Model] for this single signal using fork etc. For all other signals I am
planning of just providing RLC models as part of the [Pin] definition.

Following your discussion below from 2007 on this topic - the end points
or die pads are not defined in the [Package Model] section - hence how
can
EDA tool vendors connect the package to receiver ibis models? I am
trying
to figure out how useful this forked [Package Model] will be to our
customers? From the discussion below this point was not clear.

Thanks,

Johann

Johann Nittmann
Principal Engineer
Cavium Networks
100 Nickerson Road
Marlborough, MA 01752
Tel: 508 683 8869

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On
Behalf Of Beal, Weston
Sent: Monday, May 07, 2007 2:13 PM
To: Lynne D. Green; Yasser Sabry; ibis@server.eda-stds.org
Subject: RE: [IBIS] About Fork in The Package Model

According to the IBIS 4.2 specification FORK and ENDFORK are allowed in
package models. I haven't seen them used in package models in a long
time.
The only use I saw for FORK in a package model was to represent the
plating traces in ceramic PGA packages. That's been a few years ago.
So the answer to the original question is that the branch didn't go
anywhere. In the actual finished package the plating traces were just
stubs off the signal trace. They needed to be modeled correctly because
of
the impedance discontinuity that they created.

Regards,
Weston

-----Original Message-----
From: owner-ibis@server.eda.org [mailto:owner-ibis@server.eda.org] On
Behalf Of Lynne D. Green
Sent: Monday, May 07, 2007 9:42 AM
To: 'Yasser Sabry'; ibis@server.eda-stds.org
Subject: RE: [IBIS] About Fork in The Package Model

Hello, Yasser,

FORK and ENDFORK not allowed in PKG models.
FORK and ENDFORK are allowed in EBD and ICM models.

- Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Yasser
Sabry
Sent: Sunday, May 06, 2007 9:11 AM
To: ibis@eda-stds.org
Subject: [IBIS] About Fork in The Package Model

Hi all,

Fork is used to make branches. In EBD, it is clear where these branches
go
to as the destination node or pin is specified. However, in package
model
the destination is not clear for me. Where do the branches go to?

Thanks for your help,
Yasser Sabry

-------------------------------------------
Yasser Mohammed Sabry
Device Modeling Team
Analog/Mixed Signal - DSM Division
Mentor Graphics Egypt
Tel: (+202) 416 3613
Mob: (+2010) 1834833
Fax: (+202) 418 6945
E-mail: yasser_sabry@mentor.com
-------------------------------------------

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