RE: [IBIS] Miller Capacitance

Lynne,

You might be referring to slide 7 in this presentation:

http://www.eda.org/ibis/summits/jun03b/muranyi1.pdf

which gives an illustration on how the waveform on the
gate of the output transistor changes due to Miller
capacitance. But this presentation actually states that
this feedback is assumed to be negligible in the IBIS
behavioral buffer models and it is ignored in the model
algorithm shown in this presentation.

Amit,

What Miller capacitance are you referring to? Are you
talking about the same one the above presentation mentions?

Thanks,

Arpad
============================================================

-----Original Message-----
From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Lynne D. Green
Sent: Friday, July 06, 2012 12:21 PM
To: Amit KUMAR STE
Cc: ibis@eda.org
Subject: Re: [IBIS] Miller Capacitance

Hello, Amit,

As I remember, Arpad Muranyi has done at least one
Summit presentation on this. Topics generally
include input effects on output waveforms, input
edge-rate sensitivity.

The way I have handled this: capture
transistor-level circuit containing 2-3 preceding
stages on chip plus the selected I/O buffer. Use
this in simulations for generating the IBIS
waveform tables.

Hope this helps.

Lynne

"IBIS training when you need it, where you need it."

Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@mindspring.com

On 7/6/2012 2:18 AM, Amit KUMAR STE wrote:
> Hello Experts,
>
> Is there any way of taking miller capacitance into picture while doing ibis model of a simple single ended buffer?
> Please suggest me any presentation/document which I can refer for the same.
>
> Regards
> Amit
>

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Received on Fri Jul 6 10:55:59 2012