RE: [IBIS] IBIS-ISS Package Modeling : The Physics of a Package Model

Romi,

The intent is for the IBIS-ISS packaging solution to define SPICE subckts
between the package pins and the die. IBIS-ISS is a subset of HSPICE that
includes all of the SPICE elements required to model interconnect and
passive devices. What you are requesting will fall out.

Walter

From: Romi Mayder [mailto:romi.mayder@xilinx.com]
Sent: Monday, July 23, 2012 3:33 PM
To: Walter Katz; ibis@eda.org
Subject: RE: [IBIS] IBIS-ISS Package Modeling : The Physics of a Package
Model

Hi Walter, Arpad,

I am interested in expanding the definition below of the package to
include passive elements mounted on the substrate such as discrete
decoupling capacitors, series inductors, etc . . .

In light of IBIS v5.0 supporting BIRDs 95/98, I believe that any new
package modeling BIRDs should include explicit support for the Pull_Up and
Power_Clamp nodes.

Kind Regards

Romi

From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Walter
Katz
Sent: Friday, July 20, 2012 1:27 PM
To: ibis@eda.org
Subject: [IBIS] IBIS-ISS Package Modeling : The Physics of a Package Model

All,

Rather than discussing the possible IBIS solutions for package models, I
would like to describe the physics of the problem, and then ask some
questions of what part of the physics need to be implemented.

I would like to frame these questions with an example:

Package

150 VDD Pins

150 VSS Pins

100 Single Ended Channel Pins

Die Bump Pads

200 VDD Bump Pads

200 VSS Bump Pads

100 Single Ended Channel Bump Pads

Die Buffer Pads

100 VDD Buffer Pads

100 VSS Buffer Pads

100 Single Ended Channel Buffer Pads

Complete Package Model (describes the full physics of the package
interconnect)

150 VDD Pins

150 VSS Pins

100 Single Ended Channel Pins

200 VDD Bump Pads

200 VSS Bump Pads

100 Single Ended Channel Bump Pads

900 total ports

Complete On-Die Model (describes the full physics of the die interconnect)

200 VDD Bump Pads

200 VSS Bump Pads

100 Single Ended Channel Bump Pads

100 VDD Buffer Pads

100 VSS Buffer Pads

100 Single Ended Channel Buffer Pads

A Full Simulation will consist of

Board and all of the stuff on the Board

1 Package model instance

1 on-die model instance

100 IBIS buffers

Connections that need to be rectified

400 connections between Board and Package Model

500 connections between Package Model and On-Die Model

300 connections between On-Die Model and 100 Buffer Models

Questions to IC Vendors:

Is this setup is a completer representation of the problem?

Is it practical to produce the Package Model and On-Die Model in this
level of detail?

Do you want/need to use a subset of the on-die VDD and VSS Bump Pads in
your On-Die Model?

Do you want to be able to represent the VDD and VSS Bump Pads as two
nodes?

Do you already include the interconnect between the Channel Bump Pads and
Channel Buffer Pads in your Buffer Model?

Do you need interconnect between VDD and VSS Bump Pads and VDD and VSS
Buffer Pads, or is it sufficient to "tie" each VDD and VSS Buffer Pad to
specific VDD and VSS Bump Pads.

Do you want to be able to distribute Package and On-Die Models for slices
(subsets) of the 100 Channels?

Do you want to be able to distribute multiple Package and On-Die Models
with different combinations of the choices above?

Walter

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Received on Mon Jul 23 13:00:51 2012