[IBIS] Asian IBIS Summit (Hsinchu) - Agenda

From: Bob Ross <bob@teraspeed.com>
Date: Sat Oct 20 2012 - 17:30:43 PDT
All:

 

We have a full program with ten presentations  Registration

information is at the bottom  We are looking forward to seeing

you at the meeting.

 

Best Regards,

Lance and Bob

 

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       A S I A N   I B I S   S U M M I T    I N F O R M A T I O N

 

Time/Date:  8:00 - 16:30, Tuesday November 13, 2012

 

Location:   Ambassador Hotel Hsinchu

            No.188 Section 2, Chung Hwa Road

            Hsinchu 300, Taiwan

 

Rooms:      Ballroom D (look for signs)

 

Sponsors:   ANSYS

            Agilent Technologies

            Avant Technology (IO Methodology)

            Cadence Design Systems

            Intel Corporation

 

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          I B I S  S U M M I T  M E E T I N G  A G E N D A

 

8:15    SIGN IN

          - Vendor Tables Open at 8:30

 

9:00    Welcome

          - Lance Wang

            (Vice Chair IBIS Open Forum, IO Methodology, USA)

          - Daniel Chang (ANSYS, ROC)

 

9:15    Electronic Interconnect Challenges

          Steven Pytel (ANSYS, USA)

 

9:30    IBIS 5.1: An Overview

          Michael Mirmak (Intel Corporation, USA)

 

9:55    BREAK (Refreshments and Vendor Tables)

 

10:20   Using Latency Insertion Method to Handle IBIS Models

          Ping Liu*#, Jilin Tan*##, and Jose Schutt-Aine**

          (*Cadence Design Systems, #PRC, ##USA and

          **University of Illinois, USA)

 

10:55   IBIS-AMI, Industry Adoption, and Current Challenges

          Naijen Hsuan and TingHao Yeh (ANSYS, ROC)

 

11:25   Efficient End-to-end Simulations of 25G Optical Links

          Jing-Tao Liu*#, Fangyi Rao*##, Sanjeev Gupta** and

          Amolak Badesha** (*Technologies, #PRC, ##USA; and

          **Avago Technologies, USA)

 

12:00   FREE BUFFET LUNCH (Hosted by Sponsors)

          - Vendor Tables

 

13:30   Chip PDN Model for Power Aware Signal Integrity Analysis

          Jack W.C. Lin# and Raymond Y. Chen##

          (Cadence Design Systems, #ROC, ##USA)

 

14:00   IBIS Parser Update

          Bob Ross (Teraspeed Consulting Group, USA)

 

14:25   IBIS Validation Method Review

          Lance Wang (IO Methodology, USA)

 

14:50   BREAK (Refreshments and Vendor Tables)

 

15:15   The Evolution of DDR Memory and Overcoming Challenges of

        DDR3/4 Design

          Steven Pytel (ANSYS, USA)

 

15:50   Designing DDR3 System Using Static Timing Analysis in

        Conjunction with IBIS Simulations

          Taranjit Kukal#, Zhangmin Zhong##, and Heiko Dudek###

          (Cadence Design Systems, #India, ##China, ###Germany)

 

16;25   Concluding Items

 

16:30   END OF IBIS SUMMIT MEETING

 

------------------------------------------------------------------

 

To Register by November 6, 2012:

 

     Name:

     E-mail address:

 

     Company:

     Top-level Web Link:

 

     Country:

     Telephone:

 

   Send to BOTH:

 

     Bob Ross, Teraspeed Consulting Group    bob@teraspeed.com

     Lance Wang, IO Methodology              lwang@iometh.com

 

 

 

--

Bob Ross

Teraspeed Consulting Group, LCC

http://www.teraspeed.com

bob@teraspeeed.com

Direct : 503-246-8048

Teraspeed Labs: 503-430-1065

Headquarters: 401-284-1827

 

Teraspeed is a registered service mark of Teraspeed Consulting Group LLC

 


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Received on Sat Oct 20 17:31:18 2012

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