Re: [IBIS-Users] question regarding LVDS buffer validation

From: Andrew Ingraham <a.ingraham_at_.....>
Date: Sat Jun 04 2005 - 08:20:15 PDT
It is interesting to note that the output pulsewidth of the SPICE netlist,
is much wider than the "D" input pulsewidth.  Therefore, your SPICE model
appears to have a sizeable delay asymmetry in it, which may be missing from
your IBIS model.  By very quick inspection, your V-T tables don't seem to
have the same asymmetry.  Were the rising and falling tables
time-coordinated with one another?

Two other things you might try doing:

(1) What happens if you use wider pulses on the "D" stimulus input?  There
could be some interaction going on, due to the fact that the stimulus
pulsewidth is less than the length of the V-T tables; i.e., the buffers are
being told to switch before they have completed "playing back" the previous
transition.  Many simulators have problems doing that.

Alternatively, just invert the "D" input, and see if it is the second
transition or just the falling "D" edge that always has the trouble.

(2) Presumably this "D" input, or something like it, is being applied to
both the SPICE model and the IBIS model in your simulator.  Try using much
faster edges on the "D" input waveform.  IBIS models have no knowledge of
input edge rates, their inputs are binary (either Low or High).  Having slow
edges increases ambiguity because "slicing" happens at some point on the
waveform, which almost definitely differs between the SPICE and IBIS models.
IBIS itself has no concept of threshold (or switching reference) voltage,
but your simulator is probably using something when it slices the "D"
signal, and it's probably not the same threshold as your SPICE model.

Regards,
Andy


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Received on Sat Jun 4 08:20:22 2005

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